MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
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Any time a reset is generated, the CE transmission gate
remains disabled and CE IN remains high impedance
(regardless of CE IN activity) for the reset timeout peri-
od. When the CE transmission gate is enabled, the
impedance of CE IN appears as a 40Ω resistor in series
with the load at CE OUT. The propagation delay
through the CE transmission gate depends on V
CC
, the
source impedance of the drive connected to CE IN,
and the loading on CE OUT (see Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and a 50pF load
capacitance (Figure 7). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low-output-impedance driver.
Chip-Enable Output (MAX818)
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to a 40Ω resistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pull-up con-
nects CE OUT to OUT (Figure 5). This pull-up turns off
when the transmission gate is enabled.
Power-Fail Comparator
(MAX817/MAX819)
The MAX817/MAX819 PFI input is compared to an inter-
nal reference. If PFI is less than the power-fail threshold
(V
PFT
), PFO goes low. The power-fail comparator is
intended for use as an undervoltage detector to signal a
failing power supply (Figure 8). However, the comparator
does not need to be dedicated to this function because it
is completely separate from the rest of the circuitry.
The power-fail comparator turns off and PFO goes low
when V
CC
falls below V
BATT
. During the reset timeout
period (t
RP
), PFO is forced high, regardless of the state
of V
PFI
(see Battery Freshness Seal section). If the com-
parator is unused, connect PFI to ground and leave PFO
unconnected. PFO can be connected to MR on the
MAX819 so that a low voltage on PFI will generate a
reset (Figure 9). In this configuration, when the monitored
voltage causes PFI to fall below V
PFT
, PFO pulls MR low,
causing a reset to be asserted. Reset remains asserted
as long as PFO holds MR low, and for t
RP
(200ms) after
PFO pulls MR high when the monitored supply is above
the programmed threshold. When PFO is connected to
MR, it is not possible to enable the battery freshness
seal. Enabling the battery freshness seal requires MR to
be high or open. Once the battery freshness seal is
enabled, it is no longer affected by PFO’s connection to
MR.
Figure 7. CE Propagation Delay Test Circuit
