CSP2510DPGG Datasheet CSP2510DPG, CSP2510DPGG8, CSP2510DPGGI | P1-P3

0°C TO 85°C TEMPERATURE RANGE

IDTCSP2510D

3.3V PHASE-LOCK LOOP CLOCK DRIVER

OCTOBER 2001

2001 Integrated Device Technology, Inc. DSC-5874/3c

IDTCSP2510D

ºº

ºC TO 85

ºº

ºC TEMPERATURE RANGE

3.3V PHASE-LOCK LOOP

CLOCK DRIVER

ZERO DELAY BUFFER

DESCRIPTION:

The CSP2510D is a high performance, low-skew, low-jitter, phase-lock

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency

and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CSP2510D

operates at 3.3V.

One bank of ten outputs provide low-skew, low-jitter copies of CLK.

Output signal duty cycles are adjusted to 50 percent, independent of the duty

cycle at CLK. The outputs can be enabled or disabled via the control G input.

When the G input is high, the outputs switch in phase and frequency with

CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CSP2510D does not require

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CSP2510D requires a

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as

following any changes to the PLL reference or feedback signals. The PLL

can be bypassed for the test purposes by strapping AVDD to ground.

The CSP2510D is specified for operation from 0°C to +85°C. This device

is also available (on special order) in Industrial temperature range (-40°C

to +85°C). See ordering information for details.

PLL

FBIN

CLK

FBOUT

FUNCTIONAL BLOCK DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

• Distributes one clock input to one bank of ten outputs

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

• No external RC network required for PLL loop stability

• Operates at 3.3V VDD

• tpd Phase Error at 166MHz: < ±150ps

• Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz

• Spread Spectrum Compatible

• Operating frequency 50MHz to 175MHz

• Available in 24-Pin TSSOP package

APPLICATIONS:

• SDRAM Modules

• PC Motherboards

• Workstations

0°C TO 85°C TEMPERATURE RANGE

IDTCSP2510D

3.3V PHASE-LOCK LOOP CLOCK DRIVER

PIN CONFIGURATION

TSSOP

TOP VIEW

CLK

AVDD

VDD

GND

VDD

FBIN

AGND

VDD

GND

VDD

FBOUT

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Max Unit

VDD Supply Voltage Range –0.5 to +4.6 V

(1)

Input Voltage Range –0.5 to +6.5 V

(1,2)

Voltage range applied to any –0.5 to VDD + 0.5 V

output in the high or low state

IK Input clamp current –50 mA

(VI <0)

OK Terminal Voltage with Respect ±50 mA

O <0 or to GND (inputs VIH 2.5, VIL 2.5)

VO > VDD)

O Continuous Output Current ±50 mA

(VO = 0 to VDD)

VDD or GND Continuous Current ±100 mA

TSTG Storage Temperature Range – 65 to +150 °C

J Junction Temperature +150 ° C

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

3. The maximum package power dissipation is calculated using a junction temperature

of 150°C and a board trace length of 750 mils.

CAPACITANCE

NOTE:

1. Unused inputs must be held HIGH or LOW to prevent them from floating.

Parameter Description Min. Typ. Max. Unit

CIN Input Capacitance ⎯ 5 ⎯ pF

VI = VDD or GND

CO Output Capacitance ⎯ 6 ⎯ pF

VO = VDD or GND

CL Load Capacitance ⎯ 30 ⎯ pF

RECOMMENDED OPERATING CONDITIONS

Symbol Description Min. Max. Unit

VDD, AVDD Power Supply Voltage 3 3.6 V

TA Operating Free-Air Temperature 0 +85 °C

0°C TO 85°C TEMPERATURE RANGE

IDTCSP2510D

3.3V PHASE-LOCK LOOP CLOCK DRIVER

STATIC FUNCTION TABLE (AVDD = 0V)

DYNAMIC FUNCTION TABLE (AVDD = 3.3V)

PIN DESCRIPTION

Terminal

Name No. Type Description

CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CSP2510D clock driver. CLK is used to provide the reference signal

to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase

lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback

signal to its reference signal.

FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The

integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.

G 11 I Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When

G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.

FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to

FBIN, FBOUT completes the feedback loop of the PLL.

Y (0:9) 3, 4, 5, 8, 9, O Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be

15, 16, 17, disabled to a logic-low state by de-asserting the G control input.

20, 21

AVDD 23 Power Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL

for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.

AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.

VDD 2, 10, 14, 22 Power Power supply

GND 6, 7, 18, 19 Ground Ground

Inputs Outputs

G CLK Y (0:9) FBOUT

LL L L

LH L H

HH H H

HL L L

H running running running

Inputs Outputs

G CLK Y (0:9) FBOUT

XL L L

L running L running in

phase with CLK

LH L H

H running running in running in

phase with CLK phase with CLK

HH H H

P1-P3 P4-P6 P7-P9

CSP2510DPGG

Mfr. #:

Buy CSP2510DPGG

Manufacturer:

Description:

IC CLK DVR PLL ZDB 1:10 24TSSOP

Lifecycle:

New from this manufacturer.

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CSP2510DPGG

CSP2510DPGG

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