PRODUCT SPECIFICATION FAN5009
REV. 1.0.5 7/22/04
5
Electrical Specifications
(continued)
NOTES:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. AC Specifications guaranteed by design/characterization (not production tested).
3. For propagation delays, “tpdh” refers to low-to-high signal transition and “tpdl” refers to high-to-low signal transition
4. Transition times are defined for 10% and 90% of DC values
Figure 3. Output Disable Timing
Figure 4. Adaptive Gate Drive Timing
Parameter Symbol Conditions Min. Typ. Max. Units
Low-Side Driver
Output Resistance, Sourcing
Current
R
LUP
3.4 4.0
Ω
Output Resistance, Sinking
Current
R
LDN
1.4 1.8
Ω
Transition Times
2,4
t
R(LDRV)
See Figure 2 40 50 ns
t
F(LDRV)
20 30 ns
Propagation Delay
2,3
t
pdh(LDRV)
See Figures 2, 4 20 30 ns
t
pdl(LDRV)
25 40 ns
t
pdh(ODRV)
See Adaptive Gate
Drive Circuit
description
240 ns
V
IL(OD)
t
pdl(OD)
V
IH(OD)
t
pdh(OD)
LDRV / HDRV
OD
V
IH(PWM)
t
pdl(LDRV)
LDRV
PWM
HDRV-SW
1.2V
V
IL(PWM)
t
pdl(HDRV)
2.2V
t
pdh(LDRV)
SW
t
pdh(HDRV)