Technical Note
10/15
BD3507HFV
www.rohm.com
2010.05 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
About heat loss
In designing heat, operate the apparatus within the following conditions.
(Because the following temperatures are warranted temperature, be sure to take margin, etc. into account.)
1. Ambient temperature Ta shall be not more than 100°C.
2. Chip junction temperature Tj shall be not more than 150°C.
Chip junction temperature Tj can be considered under the following two cases.
When multilayer substrates are used, if any GND pattern is present in the inner layer, arrange heat radiation vias on the
package rear side. Because the present package size is as small as 1.0 x 1.6 mm and vias are unable to be arranged in a
large quantity at the lower part of IC, the pattern is expanded as illustrated below and the number of vias is increased to
obtain superb heat radiation characteristics (the figure below is an image figure only, and the size and the quantity of vias
that match the condition must be designed into patterns).
Most of heat loss in BD3507HFV occurs at the output N-channel FET. The power lost is determined by multiplying the
voltage between VIN and Vo by the output current. Confirm the VIN and Vo voltages used and output current conditions,
and check with the thermal derating characteristics. As this IC employs the power PKG, the thermal derating characteristics
significantly depends on the pc board conditions. When designing, care must be taken to the size of a pc board to be used.
Power dissipation (W) = {Input voltage (VIN) – Output voltage (V0VREF)}×Io (averaged)
Ex.) If VIN = 1.8 volts, V0=1.2 volts, and Io (averaged)=0.5 A, the power dissipation is given by the following:
Power dissipation (W) =(1.8 volts – 1.2 volts) × 0.5 (A)
= 0.3 W
Chip junction temperature Tj is found
from IC surface temperature TC under
actual application conditions:
Tj=TC+θj-c×W
Chip junction temperature Tj is found from ambient temperature Ta:
Tj=Ta+θj-a×W
Reference value
θj-c:HVSOF6 30/W
Reference value
Single-layer substrate
(substrate surface copper foil area: less 3%)
Sing
le-l
ayer substrate
(substrate surface copper foil area:100mm
2
)
Single-layer substrate
(substrate surface copper foil area:900mm
2
)
Single-layer substrate
(substrate surface copper foil area:2500mm
2
)
Substrate size 70×70×1.6mm
3
θj-a:HVSOF6 243.9/W
147.1/W
89.3/W
73.5/W
Technical Note
11/15
BD3507HFV
www.rohm.com
2010.05 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Example of applied circuit
Specifications: High side switch of low-voltage power supply line (1.2-2.5V)
Characteristics: RON = 300 m, lo max) = 550 mA, with soft start function and overheat protection circuit equipped.
Example Circuit
Equivalent Circuit
1pin (V
CC
)
2pin (EN)
3pin (V
IN
)
4pin (Vo)
Vcc
5pin (V
REF
)
V
IN
V
CC
V
IN
V
REF
Vo
EN
GND
V
IN
ON/OFF
Ceramic Capacitor
V
O
V
CC
V
REF
R1
C1
C2 C3
C4
V
CC
Technical Note
12/15
BD3507HFV
www.rohm.com
2010.05 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Notes for use
1. Absolute maximum ratings
For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working
temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because
it is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute
maximum rating, physical safety measures are requested to be taken, such as fuses, etc.
2. GND potential
Bring the GND terminal potential to the minimum potential in any operating condition.
3. Thermal design
Consider permissible dissipation (Pd) under actual working condition and carry out thermal design with sufficient margin
provided.
4. Terminal-to-terminal short-circuit and erroneous mounting
When the present IC is mounted to a printed circuit board, take utmost care to direction of IC and displacement. In the
event that the IC is mounted erroneously, IC may be destroyed. In the event of short-circuit caused by foreign matter that
enters in a clearance between outputs or output and power-GND, the IC may be destroyed.
5. Operation in strong electromagnetic field
The use of the present IC in the strong electromagnetic field may result in maloperation, to which care must be taken.
6. Built-in thermal shutdown protection circuit
The present IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C
(standard value) and has a -15°C (standard value) hysteresis width. When the IC chip temperature rises and the TSD
circuit operates, the output terminal is brought to the OFF state. The built-in thermal shutdown protection circuit (TSD
circuit) is first and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the
IC. Consequently, never attempt to continuously use the IC after this circuit is activated or to use the circuit with the
activation of the circuit premised.
7. Capacitor across output and GND
In the event a large capacitor is connected across output and GND, when Vcc and VIN are short-circuited with 0V or GND
for some kind of reasons, current charged in the capacitor flows into the output and may destroy the IC. Use a capacitor
smaller than 1000F between output and GND.
8. Inspection by set substrate
In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a
fear of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic
measures, provide grounding in the assembly process, and take utmost care in transportation and storage. Furthermore,
when the set substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig
and be sure to turn OFF power supply to remove the jig.
9. IC terminal input
The present IC is a monolithic IC and has a P substrate and P
+
isolation between elements.
With this P layer and N layer of each element, PN junction is formed, and when the potential relation is
GND>terminal A>terminal B, PN junction works as a diode, and
Terminal B>GND terminal A, PN junction operates as a parasitic transistor.
The parasitic element is inevitably formed because of the IC construction. The operation of the parasitic element gives
rise to mutual interference between circuits and results in malfunction, and eventually, breakdown. Consequently, take
utmost care not to use the IC to operate the parasitic element such as applying voltage lower than GND (P substrate) to
the input terminal.
Resistor Transistor (NPN)
N
N
N P
+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin B
C
B
E
N
GND
Pin A
Parasitic
element
Pin B
Other adjacent elements
E
B
C
GND
Parasitic
element

BD3507HFV-TR

Mfr. #:
Manufacturer:
Description:
LDO Voltage Controllers DROPOUT CHIP
Lifecycle:
New from this manufacturer.
Delivery:
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