Technical Note
4/15
BD3507HFV
www.rohm.com
2010.05 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Fig.13 Input Sequence 1
Fig.14 Input Sequence 2
Fig.18 Input Sequence 6
Fig.19 Transient Response
(0550mA/s)
Fig.20 Transient Response
(5500mA/s)
Fig.15 Input Sequence 3
Fig.16 Input Sequence 4
Fig.17 Input Sequence 5
VCC
EN
VREF
VO
VCC
EN
VREF
VO
VCC
EN
VREF
VO
VCC
EN
VREF
VO
VCC
EN
VREF
VO
VCC
EN
VREF
VO
VO
IO
VO
IO
Technical Note
5/15
BD3507HFV
www.rohm.com
2010.05 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Block Diagram
Pin Function
Pin No. Pin Name PIN Function
1 V
CC
VCC Pin
2 EN Enable Input Pin
3 V
IN
Input Voltage Pin
4 Vo Output Pin
5 V
REF
Reference Voltage Input Pin
6 GND Ground Pin
Pin Configration
+
-
UVLO
Current
Limit
EN
UVLO
TSD
EN
UVLO
UVLO
EN
UVLO
TSD
TSD
EN
EN
EN
VCC
V
REF
Enable
V
IN
V
O
V
O
GND
V
IN
Ceramic Capacitor
CL
VCC
V
REF
EN
1
2
3 4
5
6
GND
V
REF
V
O
V
CC
EN
V
IN
Technical Note
6/15
BD3507HFV
www.rohm.com
2010.05 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Block Function
AMP
An error amplifier that compares reference voltage (V
REF
) to Vo and drives Nch FET (Ron=300 m) of output. The
frequency characteristics are optimized so that ceramic capacitors can be used for output capacitors and high-speed
transient response can be achieved. The input voltage range at the AMP section is GND-2.7V and the output voltage
range of the AMP section is GND-VCC. At the time of EN OFF or UVLO, the output is brought to the LOW level and the
output NchFET is turned OFF.
EN
By the logic input pin, regulator ON/OFF is controlled. At the time of OFF, the circuit current is controlled to be 0µA to
reduce the standby current consumption of the apparatus. In addition, EN turns ON FET that can discharge V
REF
and Vo
and removes excess electric charge to prevent maloperation of IC on the load side. Since there is no electrical
connection with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input sequence.
UVLO
UVLO turned OFF output to prevent output voltage from making maloperation at the time of Vcc reduced voltage. Same
as EN, UVLO discharges VREF and Vo. When voltage exceeds the threshold voltage (TYP 3.8V), UVLO starts output.
CURRENT LIMIT
In the event the output current that exceeds the current (0.6A or more) set inside the IC flows when output is turned ON,
output voltage is attenuated to protect the IC on the load side. When current reduces, output voltage returns to the set
voltage.
SOFT START
Adding external resistor and capacitor to V
REF
pin can achieve soft-start. By the time constant that is determined by the
time constant of CR, V
REF
pin becomes dull, and output rises in synchronism with V
REF
pin. Overshoot of output voltage
or inrush current can be prevented.
VREF
VREF is a reference voltage input pin and sets output voltage. Since there is no electrical connection with the Vcc
terminal as is the case of Di for electrostatic measures, it does not depend on the input sequence.
TSD(Thermal Shut down)
In order to prevent thermal breakdown and thermal runaway of the IC, the output is turned OFF when chip temperature
becomes high. In addition, when temperature returns to the specified temperature, the output is recovered. However,
since the temperature protection circuit is originally built in to protect the IC itself, thermal design within Tj(max) is
requested.
VIN
This is a large-current supply line. The VIN terminal is connected to the rain of output NchFET. Since there is no
electrical connection with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input
sequence. However, because there is body Di of output Nch FET between VIN and Vo, there is electrical connection
(Di-connection) between VIN and Vo. Consequently, when the output is turned ON/OFF by VIN, reverse current flows
from Vo to VIN, to which care must be taken.

BD3507HFV-TR

Mfr. #:
Manufacturer:
Description:
LDO Voltage Controllers DROPOUT CHIP
Lifecycle:
New from this manufacturer.
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