DS3501
High-Voltage, NV, I
2
C POT with Temp Sensor
and Lookup Table
12 ____________________________________________________________________
minate communication so the slave will return control of
SDA to the master.
Slave address byte: Each slave on the I
2
C bus
responds to a slave address byte sent immediately fol-
lowing a START condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit. The slave
address byte of the DS3501 is shown in Figure 2.
When the R/W bit is 0 (such as in 50h), the master is
indicating it will write data to the slave. If R/W = 1 (51h
in this case), the master is indicating it wants to read
from the slave.
If an incorrect slave address is written, the DS3501
assumes the master is communicating with another I
2
C
device and ignores the communication until the next
START condition is sent.
Memory address: During an I
2
C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
I
2
C Communication
Writing a single byte to a slave: The master must gen-
erate a START condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a STOP condition. Remember the
master must read the slave’s acknowledgment during
all byte write operations.
When writing to the DS3501, the potentiometer will adjust
to the new setting once it has acknowledged the new
data that is being written, and the EEPROM (if SEE = 0)
will be written following the STOP condition at the end of
the write command. To change the setting without
changing the EEPROM, terminate the write with a repeat-
ed START condition before the next STOP condition
occurs. Using a repeated START condition prevents the
t
W
delay required for the EEPROM write cycle to finish.
Writing multiple bytes to a slave: To write multiple
bytes to a slave in one transaction, the master gener-
ates a START condition, writes the slave address byte
(R/W = 0), writes the memory address, writes up to 8
data bytes, and generates a STOP condition. The
DS3501 is capable of writing 1 to 8 bytes (1 page or
row) in a single write transaction. This is internally con-
trolled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). The first page begins at
address 00h and subsequent pages begin at multiples
of 8 (08h, 10h, 18h, etc). Attempts to write to additional
pages of memory without sending a STOP condition
between pages results in the address counter wrap-
ping around to the beginning of the present row. To
prevent address wrapping from occurring, the master
must send a STOP condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new START
condition and write the slave address byte (R/W = 0)
and the first memory address of the next memory row
before continuing to write data.
Acknowledge polling: Any time a EEPROM byte is
written, the DS3501 requires the EEPROM write time
(t
W
) after the STOP condition to write the contents of
the byte to EEPROM. During the EEPROM write time,
the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the
DS3501, which allows communication to continue as
soon as the DS3501 is ready. The alternative to
acknowledge polling is to wait for a maximum period of
t
W
to elapse before attempting to access the device.
EEPROM write cycles: The DS3501’s EEPROM write
cycles are specified in the
Nonvolatile Memory
Characteristics
table. The specification shown is at the
worst-case temperature (hot) as well as at room tem-
perature. Writing to shadowed EEPROM with SEE = 1
does not count as a EEPROM write.
Reading a single byte from a slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read opera-
tion occurs at the present value of the memory address
counter. To read a single byte from the slave, the master
generates a START condition, writes the slave address
byte with R/W = 1, reads the data byte with a NACK to
indicate the end of the transfer, and generates a STOP
condition. However, since requiring the master to keep
track of the memory address counter is impractical, the
following method should be used to perform reads from
a specified memory location.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-
tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates a
STOP condition.
See Figure 4 for a read example using the repeated
START condition to specify the starting memory location.
