REV. A
AD8186/AD8187
–13–
The AD8187
The AD8187 uses on-chip feedback resistors to realize the gain-
of-two function. To provide low crosstalk and a high output
impedance when disabled, each set of 500 feedback resistors is
terminated by a dedicated reference buffer. A reference buffer is
a high speed op amp configured as a unity-gain follower. The
three reference buffers, one for each channel, share a single, high
impedance input, the V
REF
pin (see Figure 4). V
REF
input bias
current is typically less than 2 µA.
A0
B0
V
REF
5V
5V
5V
GBUF 0
5V
GBUF 1
5V
GBUF 2
500
500
OUT 0
500 500
500 500
VF-1
VF-2
1
VFO
OUT1
OUT2
Figure 4. Conceptual Diagram of a Single
Multiplexer Channel, G = +2
This configuration has a few implications for single-supply
operation:
1) On the AD8187, V
REF
may not be tied to the most negative
analog supply, V
EE
.
Limits on Reference Voltage (AD8187, see Figure 5):
VVVVV
VV Von V / V Supplies
EE REF CC
REF
+<<
<<
13 16
13 34 0 5
.–.
..
A0
V
REF
5V
5V
OUT 0
5V
5V
1.3V
1.3V
1.6V
1.3V
V
OUT
V
O_MAX
= 3.7V
V
O_MAX
= 3.4V
V
O_MIN
= 1.3V
V
O_MIN
= 1.3V
V
REF
GND
GND
Figure 5. Output Compliance of Main Amplifier
Channel and Ground Buffer
2) Signal at the V
REF
pin appears at each output. Therefore,
V
REF
should be tied to a well bypassed, low impedance source.
Using superposition, it is easily shown that
VVV
OUT IN REF
2–
3) To maximize the output dynamic range, the reference voltage
should be chosen with some care.
For example, consider amplifying a 700 mV video signal with a
sync pulse 300 mV below black level. The user might decide to set
V
REF
at black level to preferentially run video signals on the faster
NPN transistor path. The AD8186 would, in this case, allow a
reference voltage as low as 1.3 V + 300 mV = 1.6 V. If the AD8187
is used, the sync pulse would be amplified to 600 mV. Therefore,
the lower limit on V
REF
becomes 1.3 V + 600 mV = 1.9 V. For
routing RGB video, an advantageous configuration would be to
employ +3 V and –2 V supplies, in which case V
REF
could be
tied to ground.
If system considerations prevent running the multiplexer on split
supplies, a false ground reference should be employed. A low
impedance reference may be synthesized with a second opera-
tional amplifier. Alternately, a well bypassed resistor divider
may serve. Refer to the Application section for further explana-
tion
and more examples.
V
REF
1F
5V
GND
OP21
100k
10k
0.022F
100
1F
FROM 1992 ADI AMPLIFIER
APPLICATIONS GUIDE
Figure 6a. Synthesis of a False Ground Reference
V
REF
1F
5V
10k
10k
CAP MUST BE LARGE
ENOUGH TO ABSORB
TRANSIENT CURRENTS
WITH MINIMUM BOUNCE.
Figure 6b. Alternate Method for Synthesis of a
False Ground Reference
High Impedance Disable
Both the AD8186 and the AD8187 may have their outputs
disabled to a high impedance state. In the case of the AD8187,
the reference buffers also disable to a state of high output
impedance. This feature prevents the feedback network of a
disabled channel from loading the output, which is valuable
when busing together the outputs of several muxes.
REV. A–14–
AD8186/AD8187
AC-Coupled Inputs (DC Restore before Mux Input)
Using ac-coupled inputs presents an interesting challenge for video
systems operating from a single 5 V supply. In NTSC and PAL
video systems, 700 mV is the approximate difference between the
maximum signal voltage and black level. It is assumed that sync
has been stripped. However, given the two pathological cases
shown in Figure 7, a dynamic range of twice the maximum signal
swing is required if the inputs are to be ac-coupled. A possible
solution would be to use a dc restore circuit before the mux.
V
REF
+700mV
V
AVG
+5 V
V
SIGNAL
GND
V
INPUT
= V
REF
+ V
SIGNAL
V
REF
~ V
AVG
V
REF
IS A DC VOLTAGE
SET BY THE RESISTORS
BLACK LINE WITH WHITE PIXEL
–700mV
WHITE LINE WITH BLACK PIXEL
V
AVG
V
REF
Figure 7. Pathological Case for
Input Dynamic Range
Tolerance to Capacitive Load
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance of R
EFF
=
(R
L
r
O
), where R
L
is the discrete resistive load, and r
O
is the open-
loop output impedance, approximately 15 for these muxes.
The load pole, at f
LOAD
= 1/(2 R
EFF
C
L
), can seriously degrade
phase margin and therefore stability. The old workaround is to
place a small series resistance directly at the output to isolate the
load pole. While effective, this ruse also affects the dc and termina-
tion characteristics of a 75 system. The AD8186 and AD8187
are built with a variable compensation scheme that senses the
output reactance and trades bandwidth for phase margin, ensuring
faster settling and lower overshoot at higher capacitive loads.
Secondary Supplies and Supply Bypassing
The high current output transistors are given their own supply
pins (Pins 15, 17, 19, and 21) to reduce supply noise on-chip
and to improve output isolation. Since these secondary, high
current supply pins are not connected on-chip to the primary
analog supplies (V
CC
/V
EE
, Pins 6, 7, 9, 11, 13, and 24), some
care should be taken to ensure that the supply bypass capacitors
are connected to the correct pins. At a minimum, the primary
supplies should be bypassed. Pin 6 and Pin 7 may be a convenient
place to accomplish this. Stacked power and ground planes could
be a convenient way to bypass the high current supply pins.
IN0A
D
GND
V
REF
OUT 0
OUT 1
OUT 2
IN1A
IN2A
IN2B
IN1B
IN0B
V
CC
V
EE
V
EE
V
EE
V
CC
OE
SEL A/B
V
EE
V
CC
V
CC
V
CC
V
EE
DV
CC
MUX0
MUX1
MUX2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1F
0.1F
Figure 8. Detail of Primary and Secondary Supplies
Split-Supply Operation
Operating from split supplies (e.g., +3 V/–2 V or ±2.5 V) simpli-
fies the selection of the V
REF
voltage and load resistor termination
voltage.
In this case, it is convenient to tie V
REF
to ground.
The logic
inputs are level shifted internally to allow the digital
supplies and
logic inputs to operate from 0 V and 5 V when
powering the
analog circuits from split supplies. The maximum
voltage difference between DV
CC
and V
EE
must not exceed 8 V
(see Figure 9).
DV
CC
(+5)
D
GND
SPLIT-SUPPLY OPERATION
DIGITAL SUPPLIES
(0V)
8V MAX
ANALOG SUPPLIES
(+2.5)
(–2.5)
V
CC
V
EE
Figure 9. Split-Supply Operation
REV. A
AD8186/AD8187
–15–
APPLICATION
Single-Supply Operation
The AD8186/AD8187 are targeted mainly for use in single-
supply 5 V systems. For operating on these supplies, both V
EE
and D
GND
should be tied to ground. The control logic pins will
be referenced to ground. Normally, the DV
CC
supply should be
set to the same positive supply as the driving logic.
For dc-coupled single-supply operation, it is necessary to set an
appropriate input dc level that is within the specified range of the
amplifier. For the unity-gain AD8186, the output dc level will
be the same as the input, while for the gain-of-two AD8187, the
V
REF
input can be biased to obtain an appropriate output dc level.
Figure 10 shows a circuit that provides a gain-of-two and is
dc-
coupled. The video input signals must have a dc bias
from their source of approximately 1.5 V. This same volt-
age is
applied to V
REF
of the AD8187. The result is that when
the
video signal is at 1.5 V, the output will also be at the
same
voltage. This is close to the lower dynamic range of
both the input and the output.
When the input goes most positive, which is 700 mV above the
black level for a standard video signal, it reaches a value of 2.2 V
and there is enough headroom for the signal. On the output
side, the magnitude of the signal will change by 1.4 V, which
will make the maximum output voltage 2.2 V + 1.4 V = 3.6 V.
This is just within the dynamic range of the output of the part.
AC Coupling
When a video signal is ac-coupled, the amount of dynamic range
required to handle the signal can potentially be double that
required for dc-coupled operation. For the unity-gain AD8186,
there is still enough dynamic range to handle an ac-coupled,
standard video signal with 700 mV p-p amplitude.
If the input is biased at 2.5 V dc, the input signal can potentially go
700 mV both above and below this point. The resulting 1.8 V and
2.2 V are within the input signal range for single 5 V operation.
Since the part is unity-gain, the outputs will follow the inputs,
and there will be adequate range at the output as well.
When using the gain-of-two AD8187 in a simple ac-coupled
application, there will be a dynamic range limitation at the output
caused by its higher gain. At the output, the gain-of-two will
produce a signal swing of 1.4 V, but the ac coupling will double
this required amount to 2.8 V. The AD8187 outputs can only
swing from 1.4 V to 3.6 V on a 5 V supply, so there are only
2.2 V of dynamic signal swing available at the output.
A standard means for reducing the dynamic range requirements
of an ac-coupled video signal is to use a dc restore. This circuit
works to limit the dynamic range requirements by clamping the
black level of the video signal to a fixed level at the input to the
amplifier. This prevents the video content of the signal from
varying the black level as happens in a simple ac-coupled circuit.
After ac coupling a video signal, it is always necessary to use a
dc restore to establish where the black level is. Usually, this
appears at the end of a video signal chain. This dc restore circuit
needs to have the required accuracy for the
system. It compen-
sates for all the offsets of the preceding
stages. Therefore, if a
dc restore circuit is to be used only for dynamic-range limiting,
it does not require great dc accuracy.
D
GND
V
EE
RED
GRN
BLU
IN2B
IN1B
IN0B
IN0A
REDA
IN1A
GRNA
IN2A
BLUA
V
REF
5V
1.5V
3.48k
1.5k
BLUB
GRNB
REDB
DV
CC
3V TO 5V
BLACK
LEVEL
TYPICAL OUTPUT LEVELS
(ALL 3 OUTPUTS)
3.0V
1.4V MAX
1.5V
BLACK
LEVEL
2.2V
1.5V
0.7V MAX
TYPICAL INPUT LEVELS
(ALL 6 OUTPUTS)
SEL A/B
OE
2
OUT0
OUT1
OUT2
V
CC
5V
AD8187
2
2
Figure 10. DC-Coupled (Bypassing and Logic Not Shown)

AD8187ARUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 480MHz SGL Supply Triple 2:1 Buffered
Lifecycle:
New from this manufacturer.
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