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Z86E2116PSC

P1-P3P4-P6P7-P9P10-P12
10
AC CHARACTERISTICS
Additional Timing Diagram
Clock
1
3
4
5
2 2 3
T
IRQ
IN
N
Additional Timing
AC CHARACTERISTICS
Additional Timing Table
T
A
= 0°C to 70°CT
A
= -40°C to 105°C
12 MHz 16 MHz 12 MHz 16 MHz
No Symbol Parameter Max Min Max Min Max Min Max Min Units Notes
1 TpC Input Clock Period 83 1000 62.5 1000 83 1000 62.5 1000 ns [1]
2 TrC,TfC Clock Input Rise & Fall Times 15 10 15 10 ns [1]
3 TwC Input Clock Width 37 21 37 21 ns [1]
4 TwTinL Timer Input Low Width 75 50 75 50 ns [2]
5 TwTinH Timer Input High Width 3TpC 3TpC 3TpC 3TpC [2]
6 TpTin Timer Input Period 8TpC 8TpC 8TpC 8TpC [2]
7 TrTin,TfTin Timer Input Rise & Fall Times 100 100 100 100 ns [2]
8A TwIL Interrupt Request Input Low Times 70 50 70 50 ns [2,4]
8B TwIL Interrupt Request Input Low Times 3TpC 3TpC 3TpC 3TpC [2,5]
9 TwIH Interrupt Request Input High Times 3TpC 3TpC 3TpC 3TpC [2,3]
Notes:
[1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0.
[2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0.
[3] Interrupt references request via Port 3.
[4] Interrupt request via Port 3 (P31-P33).
[5] Interrupt request via Port 30.
11
AC CHARACTERISTICS
Handshake Timing Diagrams
Data In
1 2
3
4 5 6
/DAV
(Input)
RDY
(Output)
Next Data In Valid
Delayed RDY
Delayed DAV
Data In Valid
Input Handshake Timing
Data Out
/DAV
(Output)
RDY
(Input)
Next Data Out Valid
Delayed RDY
Delayed DAV
Data Out Valid
7
8 9
10
11
Output Handshake Timing
12
AC CHARACTERISTICS
Handshake Timing Table
T
A
= 0°C to 70°CT
A
= -40°C to 105°C
12 MHz 16 MHz 12 MHz 16 MHz Data
No Symbol Parameter Max Min Max Min Max Min Max Min Direction
1 TsDI(DAV) Data In Setup Time 0 0 0 0 IN
2 ThDI(DAV) Data In Hold Time 145 145 145 145 IN
3 TwDAV Data Available Width 110 110 110 110 IN
4 TdDAVI(RDY) DAV Fall to RDY Fall Delay 115 115 115 115 IN
5 TdDAVId(RDY) DAV Rise to RDY Rise Delay 115 115 115 115 IN
6 TdDO(DAV) RDY Rise to DAV Fall Delay 0 0 0 0 IN
7 TcLDAV0(RDY) Data Out to DAV Fall Delay TpC TpC TpC TpC OUT
8 TcLDAV0(RDY) DAV Fall to RDY Fall Delay 0 0 0 0 OUT
9 TdRDY0(DAV) RDY Fall to DAV Rise Delay 115 115 115 115 OUT
10 TwRDY RDY Width 110 110 110 110 OUT
11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay 115 115 115 115 OUT
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
© 1995 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
P1-P3P4-P6P7-P9P10-P12

Z86E2116PSC

Mfr. #:
Buy Z86E2116PSC
Manufacturer:
ZiLOG
Description:
IC MCU 8BIT 8KB OTP 40DIP
Lifecycle:
New from this manufacturer.
Delivery:
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