7
DC CHARACTERISTICS
T
A
= 0°CT
A
= -40°C
to +70°C to +105°C Typical
Sym. Parameter Min Max Min Max @ 25°C Units Conditions
Max Input Voltage 7 7 V I
IN
250 µA
Max Input Voltage 13 13 V P30-P33 Only
V
CH
Clock Input High Voltage 3.8 V
CC
3.8 V
CC
V Driven by External Clock Generator
V
CL
Clock Input Low Voltage -0.03 0.8 -0.03 0.8 V Driven by External Clock Generator
V
IH
Input High Voltage 2.0 V
CC
2.0 V
CC
V
V
IL
Input Low Voltage -0.3 0.8 -0.3 0.8 V
V
OH
Output High Voltage 2.4 2.4 V I
OH
= -2.0 mA
V
OL
Output Low Voltage 0.4 0.4 V I
OL
= +2.0 mA
V
RH
Reset Input High Voltage 3.8 V
CC
3.8 V
CC
V
V
Rl
Reset Input Low Voltage -0.03 0.8 -0.03 0.8 V
I
IL
Input Leakage -10 10 -10 10 µA 0V V
IN
+5.25V
I
OL
Output Leakage -10 10 -10 10 µA 0V V
IN
+5.25V
I
IR
Reset Input Current -50 -50 µAV
CC
= +5.25V, V
RL
= 0V
I
CC
Supply Current 50 50 25 mA @ 12 MHz
60 60 35 mA @ 16 MHz
I
CC1
Standby Current 15 15 5 mA HALT Mode V
IN
= OV, V
CC
@ 12 MHz
20 20 10 mA HALT Mode V
IN
= OV, V
CC
@ 16 MHz
I
CC2
Standby Current 20 20 5 µA STOP Mode V
IN
= OV, V
CC
@ 12 MHz
20 20 5 µA STOP Mode V
IN
= OV, V
CC
@ 16 MHz
Notes:
I
CC2
requires loading TMR (%F1H) with any value prior to STOP execution.
Use this sequence:
LD TMR,#00
NOP
8
R//W
9
12
19
3
16
13
4
5
8 18 11
6
17
10
15
7
14
21
Port 0, /DM
Port 1
/AS
/DS
(Read)
Port 1
/DS
(Write)
A - A
07
D - D IN
07
D - D OUT
07
A - A
07
External I/O or Memory Read/Write Timing
AC CHARACTERISTICS
External I/O or Memory Read or Write Timing Diagram
9
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
T
A
= 0°C to 70°CT
A
= -40°C to 105°C
12 MHz 16 MHz 12 MHz 16 MHz
No Symbol Parameter Max Min Max Min Max Min Max Min Units Notes
1 TdA(AS) Address Valid to /AS Rise Delay 35 20 35 25 ns [2,3]
2 TdAS(A) /AS Rise to Address Float Delay 45 30 45 35 ns [2,3]
3 TdAS(DR) /AS Rise to Read Data Req’d Valid 220 180 250 180 ns [1,2,3]
4 TwAS /AS Low Width 55 35 55 40 ns [2,3]
5 TdAZ(DS) Address Float to /DS Fall 0000ns
6 TwDSR /DS (Read) Low Width 185 135 185 135 ns [1,2,3]
7 TwDSW /DS (Write) Low Width 110 80 110 80 ns [1,2,3]
8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 130 75 130 75 ns [1,2,3]
9 ThDR(DS) Read Data to /DS Rise Hold Time 0000ns[2,3]
10 TdDS(A) /DS Rise to Address Active Delay 45 35 65 50 ns [2,3]
11 TdDS(AS) /DS Rise to /AS Fall Delay 55 30 45 35 ns [2,3]
12 TdR/W(AS) R//W Valid to /AS Rise Delay 30 20 33 25 ns [2,3]
13 TdDS(R/W) /DS Rise to R//W Not Valid 35 30 50 35 ns [2,3]
14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 35 25 35 25 ns [2,3]
15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 35 30 55 35 ns [2,3]
16 TdA(DR) Address Valid to Read Data Req’d Valid 255 200 310 230 ns [1,2,3]
17 TdAS(DS) /AS Rise to /DS Fall Delay 55 40 65 45 ns [2,3]
18 TdDI(DS) Data Input Setup to /DS Rise 75 60 75 60 ns [1,2,3]
19 TdDM(AS) /DM Valid to /AS Fall Delay 50 30 50 30 ns [2,3]
Clock Dependent Formulas
Number Symbol Equation
1 TdA(AS) 0.40TpC + 0.32
2 TdAS(A) 0.59TpC - 3.25
3 TdAS(DR) 2.38TpC + 6.14
4 TwAS 0.66TpC - 1.65
6 TwDSR 2.33TpC - 10.56
7 TwDSW 1.27TpC + 1.67
8 TdDSR(DR) 1.97TpC - 42.5
10 TdDS(A) 0.8TpC
11 TdDS(AS) 0.59TpC - 3.14
12 TdR/W(AS) 0.4TpC
13 TdDS(R/W) 0.8TpC - 15
14 TdDW(DSW) 0.4TpC
15 TdDS(DW) 0.88TpC - 19
16 TdA(DR) 4TpC - 20
17 TdAS(DS) 0.91TpC - 10.7
18 TsDI(DS) 0.8TpC - 10
19 TdDM(AS) 0.9TpC - 26.3
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics table.
Standard Test Load
All timing references use 2.0V for a logic 1 and 0.8V for a logic 0.

Z86E2116PSC

Mfr. #:
Manufacturer:
ZiLOG
Description:
IC MCU 8BIT 8KB OTP 40DIP
Lifecycle:
New from this manufacturer.
Delivery:
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