MAX199ACAI Datasheet MAX199BCAI+, MAX199BEWI+T, MAX199BCWI+T | P10-P12

MAX199

How to Start a Conversion

Conversions are initiated with a write operation, which

selects the mux channel and configures the MAX199 for

either unipolar or bipolar input range. A write pulse (WR

+ CS) can either start an acquisition interval or initiate a

combined acquisition plus conversion. The sampling

interval occurs at the end of the acquisition interval.

The ACQMOD bit in the input control byte offers two

options for acquiring the signal: internal or external.

The conversion period lasts for 12 clock cycles in either

internal or external clock or acquisition mode.

Writing a new control byte during the conversion cycle

will abort the conversion in progress and start a new

acquisition interval.

Internal Acquisition

Select internal acquisition by writing the control byte

with the ACQMOD bit cleared (ACQMOD = 0). This

causes the write pulse to initiate an acquisition interval

whose duration is internally timed. Conversion starts

when this six-clock-cycle acquisition interval (3µs with

CLK

= 2MHz) ends. See Figure 5.

External Acquisition

Use the external acquisition timing mode for precise con-

trol of the sampling aperture and/or independent control of

acquisition and conversion times. The user controls acqui-

sition and start-of-conversion with two separate write puls-

es. The first pulse, written with ACQMOD = 1, starts an

acquisition interval of indeterminate length. The second

write pulse, written with ACQMOD = 0, terminates acquisi-

tion and starts conversion on WR’s rising edge (Figure 6).

However, if the second control byte contains ACQMOD =

1, an indefinite acquisition interval is restarted.

The address bits for the input mux must have the same

values on the first and second write pulses. Power-

down mode bits (PD0, PD1) can assume new values on

the second write pulse (see

Power-Down Mode

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

10 ______________________________________________________________________________________

CSWS

ACQI

CONV

INT1

D01

HIGH-ZHIGH-Z

CSRS

CSRH

D7–D0

INT

HBEN

DOUT

ACQMOD ="0"

HIGH / LOW

BYTE VALID

HIGH / LOW

BYTE VALID

CONTROL

BYTE

CSWH



Figure 5. Conversion Timing Using Internal Acquisition Mode

Table 5. Data-Bus Output

PIN HBEN = LOW HBEN = HIGH

D0 B0 (LSB) B8

D1 B1 B9

D2 B2 B10

D3 B3 B11 (MSB)

D4 B4 B11 (BIP = 1) / 0 (BIP = 0)

D5 B5 B11 (BIP = 1) / 0 (BIP = 0)

D6 B6 B11 (BIP = 1) / 0 (BIP = 0)

D7 B7 B11 (BIP = 1) / 0 (BIP = 0)

How to Read a Conversion

A standard interrupt signal, INT, is provided to allow the

device to flag the µP when the conversion has ended

and a valid result is available. INT goes low when the

conversion is complete and the output data is ready

(Figures 5 and 6). It returns high on the first read cycle

or if a new control byte is written.

Clock Modes

The MAX199 operates with either an internal or an

external clock. Control bits (D6, D7) select either inter-

nal or external clock mode. Once the desired clock

mode is selected, changing these bits to program

power-down will not affect the clock mode. In each

mode, internal or external acquisition can be used. At

power-up, the MAX199 defaults to external clock mode.

Internal Clock Mode

Select internal clock mode to free the µP from the

burden of running the SAR conversion clock. To select

this mode, write the control byte with D7 = 0 and D6 = 1.

A 100pF capacitor between the CLK pin and ground

sets this frequency to 1.56MHz nominal. Figure 7

shows a linear relationship between the internal clock

period and the value of the external capacitor used.

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

______________________________________________________________________________________ 11

CSWS

ACQI

CONV

INT1

D01

CSHW

CSRS

CSRH

ACQMOD = "1"

D7–D0

INT

HBEN

DOUT

ACQMOD = "0"

HIGH / LOW

BYTE VALID

HIGH-Z HIGH-Z

HIGH / LOW

BYTE VALID

CONTROL

BYTE

CONTROL

BYTE



Figure 6. Conversion Timing Using External Acquisition Mode

2000

0 50 250 350

500

CLOCK PIN CAPACITANCE (pF)

INTERNAL CLOCK PERIOD (ns)

100 150 200 300

1500

1000

Figure 7. Internal Clock Period vs. Clock Pin Capacitance

MAX199

External Clock Mode

Select external clock mode by writing the control byte

with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR

timing relationships in internal and external acquisition

modes, with an external clock. A 100kHz to 2.0MHz

external clock with 45% to 55% duty cycle is required

for proper operation. Operating at clock frequencies

lower than 100kHz will cause a voltage droop across

the hold capacitor, and subsequently degrade perfor-

mance.

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

12 ______________________________________________________________________________________

CLK

WR GOES HIGH WHEN CLK IS HIGH

WR GOES HIGH WHEN CLK IS LOW

CWS

CWH

ACQUISITION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQMOD = "0"

Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)

CLK

WR GOES HIGH WHEN CLK IS HIGH

WR GOES HIGH WHEN CLK IS LOW

CWH

CWS

ACQUISITION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQMOD = "1"

ACQMOD = "0"

Figure 8b. External Clock and WR Timing (External Acquisition Mode)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX199ACAI

Mfr. #:

Buy MAX199ACAI

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12Bit 8Ch 100ksps 4.18V Precision ADC

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MAX199ACAI

MAX199ACAI

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