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MK1575-01GI

P1-P3P4-P6P7-P9P10-P12P13-P14
DATASHEET
CLOCK RECOVERY PLL MK1575-01
IDT™
CLOCK RECOVERY PLL 1
MK1575-01 REV N 121809
Description
The MK1575-01 is a clock recovery Phase-Locked Loop
(PLL) designed for clock synthesis and synchronization in
cost sensitive applications. The device is optimized to
accept a low-frequency reference clock to generate a
high-frequency data or graphics pixel clock. External loop
filter components allow tailoring of loop frequency response
characteristics. For low jitter / phase noise requirements
refer to the MK2069 products.
Features
• Long-term output jitter <2 nsec over 10 µsec period
• External PLL clock feedback path enable “zero delay” I/O
clock skew configuration
• Selectable internal feedback divider provides popular
telecom and video clock frequencies (see tables below)
• Can optionally use external feedback divider to generate
other output frequencies.
• Single 3.3 V supply, low-power CMOS
• Power-down mode and output tri-state (pin OE)
• Packaged in 16-pin TSSOP
• Available in Pb (lead) free package
• Industrial temperature range available
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Pre-Configured Input/Output
Frequency Combinations:
Telecom T/E Clock Modes (rising edge aligned):
Video Clock Modes (falling edge aligned):
Block Diagram
The standard external clock feedback configuration is shown. Use this configuration for the pre-configured input/output
frequency combinations listed above.
Addr
FS2:0
Input
Clock
Output Clocks
(MHz)
Clock
Type
CLK1 CLK2
000 8 kHz 3.088 1.544 T1
001 8 kHz 16.384 2.048 E1
010 8 kHz 34.368 17.184 E3
011 8 kHz 44.736 22.368 T3
Addr
FS2:0
Input
Clock
(kHz)
Output Clocks
(MHz)
Clock
Type
CLK1 CLK2
100 15.625 54 27 PAL 601
101 15.734 54 27 NTSC 601
110 15.625 35.468 17.734 PAL 4xf
sc
111 15.734 28.636 14.318 NTSC 4xf
sc
REFIN
FBIN
CLK1
Clock Input
MUX
0
1
Charge
Pump
VCO
CHGP
VS
Divider
Phase
Detector
CHPR
MUX
0
1
C
B
R
S
C
S
FCLK
Divider
CLK2
Divider
Divider
LUT
CLK2
FCLK
FS2:0
3
External Feedback Clock Connection
OE
300 pF
MK1575-01
CLOCK RECOVERY PLL CLOCK SYNTHESIZER
IDT™
CLOCK RECOVERY PLL 2
MK1575-01 REV N 121809
Pin Assignment
16 pin 4.40 mil body, 0.65 mil pitch TSSOP
Pin Descriptions
12
1
11
2
10
REFIN
FBIN
3
9
FS0
4
VDDA
NC
5
VDDD
6
FCLK
7
FS1
8
GNDA
OE
CLK2
FS2
GNDD
CLK1
CHGP
CHPR
16
15
14
13
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 REFIN Input
Reference clock input. Connect the input clock to this pin. Can be
Rising or Falling edge triggered as per Detailed Mode Selection Table,
page 3.
2FS0Input
Frequency Selection Input bit 0, selects internal divider values as per
Detailed Mode Selection Table, page 3.
3 VDDA Power Power supply connection for internal VCO and other analog circuits.
4 VDDD Power Power supply connection for internal digital circuits and output buffers.
5FS1Input
Frequency Selection Input bit 1, selects internal divider values as per
Detailed Mode Selection Table, page 3.
6 GNDA Ground Ground connection for internal VCO and other analog circuits.
7 GNDD Ground Ground connection for internal digital circuits and output buffers.
8 CHGP — Loop filter connection, active node.
9 CHPR — Loop filter connection, reference node. Do not connect to ground.
10 CLK1 Output Output clock 1.
11 FS2 Input
Frequency Selection Input bit 2, selects internal divider values as per
Detailed Mode Selection Table, page 3.
12 CLK2 Output Output clock 2.
13 OE
Input
Output Enable, tristates CLK1, CLK2, FCLK and powers down PLL
when high. Internal pull-up.
14 FCLK Output
Feedback clock output, connect to FBIN for the pre-configured
frequency combinations listed in the tables on page 1.
15 NC — No internal connection, connect to ground.
16 FBIN Input
Feedback clock input. Connect to CLK1, CLK2, FCLK, or the output of
an external feedback divider, depending on application. Refer to
document text for more information.
MK1575-01
CLOCK RECOVERY PLL CLOCK SYNTHESIZER
IDT™
CLOCK RECOVERY PLL 3
MK1575-01 REV N 121809
Detailed Mode Selection Table
Refer to this table when not using the standard external clock feedback configuration shown on page 1.
Block Diagram, Showing Device Configuration Options
Address
FS2:0
Internal Divider Settings
FBIN, REFIN
Clock Edge
CLK1 Output
Frequency
Range
VS Divider CLK2 Divider FCLK Divider
000 64 2 386 Rising 1.5 - 5 MHz
001 16 8 2048 Rising 6 - 20 MHz
010 8 2 4296 Rising 12 - 40 MHz
011 4 2 5592 Rising 24 - 80 MHz
100 4 2 3456 Falling 24 - 80 MHz
101 4 2 3432 Falling 24 - 80 MHz
110 8 2 2270 Falling 12 - 40 MHz
111 8 2 1820 Falling 12 - 40 MHz
REFIN
FBIN
CLK1
Clock Input
MUX
0
1
Charge
Pump
VCO
CHGP
VS
Divider
Phase
Detector
CHPR
MUX
0
1
C
B
R
S
C
S
FCLK
Divider
CLK2
Divider
Divider
LUT
CLK2
FCLK
FS2:0
3
FB Divider
Optional External
Feedback Divider
Feedback Clock Options
(only connect one output)
OE
300 pF
P1-P3P4-P6P7-P9P10-P12P13-P14

MK1575-01GI

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