MK1575-01
CLOCK RECOVERY PLL CLOCK SYNTHESIZER
IDT™
CLOCK RECOVERY PLL 5
MK1575-01 REV N 121809
Setting PLL Loop Bandwidth and
Damping Factor
The frequency response of the MK1575-01 PLL may be
approximated by the following equation:
Normalized PLL Bandwidth
The associated damping factor is calculated as follows:
Damping factor,
Where:
K
O
= VCO gain in Hz/Volt
(use 340 MHz/V)
I
cp
= Charge pump current, 12.5 µA
N = Total feedback divide from VCO,
(Refer to N Value table, below)
C
S
= External loop filter capacitor in Farads
R
S
= Loop filter resistor in Ohms
The above bandwidth equation calculates the “normalized”
loop bandwidth which is approximately equal to the - 3dB
bandwidth. This approximate calculation does not take into
account the effects of damping factor or the third pole
imposed by C
P
. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on the output clocks due to modulation of
the PLL by the input reference frequency, the following
general rule should be observed:
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. For video applications, a low
damping factor (0.7 to 1.0) is generally desired for fast
genlocking. For telecom applications, a higher damping
factor is usually desirable. A higher damping factor will
create less passband gain peaking which will minimize the
gain of network clock wander amplitude. A higher damping
factor may also increase output clock jitter when there is
excess digital noise in the system application, due to the
reduced ability of the PLL to respond to, and therefore
compensate for, phase noise ingress.
Notes on setting the value of C
P
As another general rule, the following relationship should be
maintained between components C1 and C2 in the external
loop filter:
Where:
C
B
= External bypass capacitor in Farads
Note that the MK1575-01 contains an internal 300 pF filter
cap which is connected in parallel with external device C
B
.
This helps to reduce output clock jitter. In some applications
external device C
B
will not be required.
C
P
establishes a second pole in the PLL loop filter. For
higher damping factors (>1), calculate the value of C
P
based
on a C
S
value that would be used for a damping factor of 1.
This will minimize baseband peaking and loop instability that
can lead to output jitter.
C
P
also helps to damp VCO input voltage modulation
caused by the charge pump correction pulses. A C
P
value
that is too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme cases
where input jitter is high, charge pump current is high, and
C
P
is too small, the VCO input voltage can hit the supply or
ground rail resulting in non-linear loop response.
The best way to set the value of C
P
is to use the External
Loop Filter Solver located on the IDT web site.
R
S
K
O
I
CP
⋅⋅()
2π N⋅
-----------------------------------------------
=
ζ
R
S
2
--------
K
O
I
CP
C
S
⋅⋅
N
------------------------------------------
=
PLL Bandwidth
f
Phase Detector
20
--------------------------------
≤
C
P
C
S
20
------=
C
P
C
B
300 pF+=
