IS61LP6432A
IS61LP6436A ISSI
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -133
Symbol Parameter Min. Max. Min. Max. Unit
fMAX
(3)
Clock Frequency — 166 — 133 MHz
tKC
(3)
Cycle Time 6 — 7.5 — ns
tKH Clock High Time 2.4 — 2.8 — ns
tKL
(3)
Clock Low Time 2.4 — 2.8 — ns
tKQ
(3)
Clock Access Time — 3.5 — 4 ns
tKQX
(1)
Clock High to Output Invalid 3 — 3 — ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — ns
tKQHZ
(1,2)
Clock High to Output High-Z 1.5 3.5 1.5 3.5 ns
tOEQ
(3)
Output Enable to Output Valid — 3.5 — 3.8 ns
tOEQX
(1)
Output Disable to Output Invalid 0 — 0 — ns
tOELZ
(1,2)
Output Enable to Output Low-Z 0 — 0 — ns
tOEHZ
(1,2)
Output Disable to Output High-Z 2 4.5 2 5 ns
tAS
(3)
Address Setup Time 2.1 — 2.1 — ns
tSS
(3)
Address Status Setup Time 1.5 — 1.5 — ns
tWS
(3)
Write Setup Time 1.5 — 1.5 — ns
tCES
(3)
Chip Enable Setup Time 1.5 — 1.5 — ns
tAVS
(3)
Address Advance Setup Time 1.5 — 1.5 — ns
tAH
(3)
Address Hold Time 1.0 — 1.0 — ns
tSH
(3)
Address Status Hold Time 0.5 — 0.5 — ns
tWH
(3)
Write Hold Time 0.5 — 0.5 — ns
tCEH
(3)
Chip Enable Hold Time 0.5 — 0.5 — ns
tAVH
(3)
Address Advance Hold Time 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
