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IS61LP6436A-133TQ-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
IS61LP6432A
IS61LP6436A ISSI
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2
-
A15 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BW1-BW4 Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VDD +3.3V Power Supply
Vss Ground
VDDQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
NC
DQb8
DQb7
VDDQ
VSS
DQb6
DQb5
DQb4
DQb3
VSS
VDDQ
DQb2
DQb1
VSS
NC
VDD
ZZ
DQa8
DQa7
VDDQ
VSS
DQa6
DQa5
DQa4
DQa3
VSS
VDDQ
DQa2
DQa1
NC
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
GW
BWE
OE
ADS
C
ADSP
ADV
A8
A9
NC
DQc1
DQc2
VDDQ
VSS
DQc3
DQc4
DQc5
DQc6
VSS
VDDQ
DQc7
DQc8
NC
VDD
NC
VSS
DQd1
DQd2
VDDQ
VSS
DQd3
DQd4
DQd5
DQd6
VSS
VDDQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
46 47 48 49 50
64K x 32
100-Pin TQFP
IS61LP6432A
IS61LP6436A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
09/02/05
TRUTH TABLE
Address
Operation Used
CECE
CECE
CE CE2
CE2CE2
CE2CE2
CE2
ADSPADSP
ADSPADSP
ADSP
ADSCADSC
ADSCADSC
ADSC
ADVADV
ADVADV
ADV
WRITEWRITE
WRITEWRITE
WRITE
OEOE
OEOE
OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None X X H H L X X X High-Z
Deselected, Power-down None X L X H L X X X High-Z
Read Cycle, Begin Burst External L H L L XXXXQ
Read Cycle, Begin Burst External L H L H L X Read X Q
Write Cycle, Begin Burst External L H L H L X Write X D
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X D
Write Cycle, Continue Burst Next H X X X H L Write X D
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X D
Write Cycle, Suspend Burst Current H X X X H H Write X D
PARTIAL TRUTH TABLE
Function
GWGW
GWGW
GW
BWEBWE
BWEBWE
BWE
BW1BW1
BW1BW1
BW1
BW2BW2
BW2BW2
BW2
BW3BW3
BW3BW3
BW3
BW4BW4
BW4BW4
BW4
Read H H XXXX
Read H L HHHH
Write Byte 1 H L L H H H
Write All Bytes H LLLLL
Write All Bytes L XXXXX
IS61LP6432A
IS61LP6436A ISSI
®
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = Vss)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to Vss for I/O Pins –0.5 to VDDQ + 0.3 V
VIN Voltage Relative to Vss for –0.5 to VDD + 0.5 V
for Address and Control Inputs
VDD Voltage on VDD Supply Relative to Vss –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

IS61LP6436A-133TQ-TR

Mfr. #:
Buy IS61LP6436A-133TQ-TR
Manufacturer:
ISSI
Description:
SRAM 2Mb 64Kx36 133Mhz Sync SRAM 3.3v
Lifecycle:
New from this manufacturer.
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