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85214AGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-
HSTL FANOUT BUFFER
ICS85214
IDT™ / ICS™
HSTL FANOUT BUFFER 1
ICS85214AG REV. B JUNE 3, 2016
General Description
The ICS85214 is a low skew, high performance
1-to-5 Differential-to-HSTL Fanout Buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The CLK0,
CLK0
pair can accept most standard differential
input levels. The single ended CLK1 input accepts LVCMOS or
LVTTL input levels. Guaranteed output and part-to-part skew
characteristics make the ICS85214 ideal for those clock distri-
bution applications demanding well defined performance and
repeatability.
Block Diagram
Features
• Five differential HSTL compatible outputs
• Selectable differential CLK0, CLK0 or LVCMOS/LVTTL clock
inputs
• CLK0, CLK0 pair can accept the following differential input
levels: LVPECL, LVDS, HSTL, HCSL, SSTL
• CLK1 can accept the following input levels: LVCMOS or LVTTL
• Output frequency up to: 700MHz
• Translates any single-ended input signal to HSTL levels with
resistor bias on CLK0 input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.8ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 85°C ambient operating temperature
• Industrial temperature information available upon request
• Available in lead-free (RoHS 6) package
• For functional replacement part use 8523
Pin Assignment
ICS85214
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
HiPerClockS™
IC
S
0
1
D
Q
LE
0
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
CLK_EN
CLK0
CLK0
CLK1
CLK_SEL
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Q4
V
DDO
CLK_EN
V
DD
nc
CLK1
CLK0
CLK0
nc
CLK_SEL
GND
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
IDT™ / ICS™
HSTL FANOUT BUFFER 2
ICS85214AG REV. B JUNE 3, 2016
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 Q0, Q0
Output Differential output pair. HSTL interface levels.
3, 4 Q1, Q1
Output Differential output pair. HSTL interface levels.
5, 6 Q2, Q2
Output Differential output pair. HSTL interface levels.
7, 8 Q3, Q3
Output Differential output pair. HSTL interface levels.
9, 10 Q4, Q4
Output Differential output pair. HSTL interface levels.
11 GND Power Power supply ground.
12 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects differential CLK1input. When LOW,
selects CLK0, CLK0
inputs. LVCMOS/LVTTL interface levels.
13, 17 nc Unused No connect.
14 CLK0
Input Pullup Inverting differential clock input.
15 CLK0 Input Pulldown Non-inverting differential LVPECL clock input.
16 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
18 V
DD
Power Positive supply pin.
19 CLK_EN
Input Pulldown
Synchronizing clock enable. When LOW, clock outputs follow clock input.
When HIGH, Qx outputs are forced low, Qx outputs are forced high.
LVTTL/LVCMOS interface levels.
20 V
DDO
Power Output supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
IDT™ / ICS™
HSTL FANOUT BUFFER 3
ICS85214AG REV. B JUNE 3, 2016
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, CLK0 inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
Inputs Outputs
CLK_EN
Q0:Q4 Q0:Q4
0 Enabled Enabled
1 Disabled; LOW Disabled; HIGH
Inputs Outputs
Input to Output Mode PolarityCLK0 or CLK1 CLK0
Q[0:4] Q[0:4]
0 1 LOW HIGH Differential to Differential Non-Inverting
1 0 HIGH LOW Differential to Differential Non-Inverting
0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting
1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting
Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting
Enabled
Disabled
CLK0
CLK_EN
CLK0
Q0:Q4
Q0:Q4
P1-P3P4-P6P7-P9P10-P12P13-P15

85214AGLFT

Mfr. #:
Buy 85214AGLFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 5 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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