ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
IDT™ / ICS™
HSTL FANOUT BUFFER 7
ICS85214AG REV. B JUNE 3, 2016
Parameter Measurement Information, continued
Output Rise/Fall Time
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SWING
R2
1K
V
DD
CLK_IN
R1
1K
C1
0.1uF
V_REF
CLKx
nCLKx
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
IDT™ / ICS™
HSTL FANOUT BUFFER 8
ICS85214AG REV. B JUNE 3, 2016
Differential Clock Input Interface
The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/CLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3A. HiPerClockS CLK/CLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3C. HiPerClockS CLK/CLK
Input
Driven by a 3.3V LVPECL Driver
Figure 3E. HiPerClockS CLK/CLK
Input
Driven by a 3.3V HCSL Driver
Figure 3B. HiPerClockS CLK/CLK
Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/CLK
Input
Driven by a 3.3V LVDS Driver
Figure 3F. HiPerClockS CLK/CLK
Input
Driven by a 2.5V SSTL Driver
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120Ω
R2
120Ω
R3
120
Ω
R4
120
Ω
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
IDT™ / ICS™
HSTL FANOUT BUFFER 9
ICS85214AG REV. B JUNE 3, 2016
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
CLK/CLK INPUTS
For applications not requiring the use of the differential input, both
CLK and CLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK0 to
ground.
CLK INPUT
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
Outputs:
HSTL Outputs
All unused HSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Schematic Example
Figure 4 shows a schematic example of the ICS85214. In this
example, the input is driven by an IDT HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near the
power pin. For ICS85214, the unused clock outputs can be left
floating.
Figure 4. ICS85214 HSTL Buffer Schematic Example
Zo = 50 Ohm
R9
50
R11
1K
U1
ICS85214
1
2
3
4
5
6
7
8
9
1011
12
13
14
15
16
20
19
18
17
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4GND
CLK_SEL
nc
nCLK
CLK
SCLK
VDDO
nCLK_EN
VDD
nc
3.3V
Zo = 50 Ohm
R1
50
C2
0.1u
Zo = 50
R4
50
R7
50
LVHSTL Driver
R12 1K
R10
50
R3
50
Zo = 50
C1
0.1u
1.8V
Zo = 50
+
-
+
-
Zo = 50
Zo = 50
+
-
R8
50
Zo = 50
1.8V
R2
50

85214AGLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 5 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
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