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AK4103AVF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
[AK4103A]
MS0251-E-01 2009/01
- 4 -
PIN/FUNCTION
No. Pin Name I/O Description
1 V1 I Validity Bit Input Pin
2 TRANS I Audio Routing Mode (Transparent Mode) Pin at Synchronous mode
0: Normal mode, 1: Audio routing mode (transparent mode)
3 PDN I Power Down & Reset Pin (Pull-up Pin)
When “L”, the AK4103A is powered-down, TXP/N pins are “L” and the
control registers are reset to default values.
4 MCLK I Master Clock Input Pin
5 SDTI I Audio Serial Data Input Pin
6 BICK I/O Audio Serial Data Clock Input/Output Pin
Serial Clock for SDTI pin which can be configured as an output based on
the DIF2-0 inputs.
7 LRCK I/O Input/Output Channel Clock Pin
Indicates left or right channel, and can be configured as an output based on
the DIF2-0 inputs.
FS0 I Sampling Frequency Select 0 Pin at Synchronous mode (Pull-down Pin)
CSN I Host Interface Chip Select Pin at Asynchronous mode (Pull-down Pin)
8
AKMODE I AK4112B Mode Pin at Audio routing mode (Pull-down Pin)
0: Non-AKM receivers mode, 1: AK4112B mode
FS1 I Sampling Frequency Select 1 Pin at Synchronous mode (Pull-down Pin) 9
CDTI I Host Interface Data Input Pin at Asynchronous mode (Pull-down Pin)
FS2 I Sampling Frequency Select 2 Pin at Synchronous mode (Pull-down Pin) 10
CCLK I Host Interface Bit Clock Input Pin at Asynchronous mode (Pull-down Pin)
FS3 I Sampling Frequency Select 3 Pin at Synchronous mode (Pull-down Pin) 11
CDTO O Host Interface Data Output Pin at Asynchronous mode (Pull-down Pin)
12 C1 I Channel Status Bit Input Pin
13 ANS I Asynchronous/Synchronous Mode Select Pin (Pull-up Pin)
0: Asynchronous mode, 1: Synchronous mode
14 BLS I/O Block Start Input/Output Pin (Pull-down Pin)
In normal mode, the channel status block output is “H” for the first four
bytes. In audio routing mode, the pin is configured as an input. When PDN
pin = “L”, BLS pin goes “H” at Normal mode.
15 CKS0 I Clock Mode Select 0 Pin (Pull-up Pin)
16 CKS1 I Clock Mode Select 1 Pin (Pull-down Pin)
17 VDD -
Power Supply Pin, 4.75V∼5.25V
18 VSS - Ground Pin, 0V
19 TXN O Negative Differential Output Pin
20 TXP O Positive Differential Output Pin
21 DIF0 I Audio Serial Interface Select 0 Pin (Pull-down Pin)
22 DIF1 I Audio Serial Interface Select 1 Pin (Pull-down Pin)
23 DIF2 I Audio Serial Interface Select 2 Pin (Pull-down Pin)
24 U1 I User Data Bit Input Pin for Channel 1 (Pull-down Pin)
Note 1. Internal pull-up and pull-down resistors are connected on-chip. The value of the resistors is 43kΩ (typ).
Note 2. All input pins except internal pull-down/pull-up pins should not be left floating.
[AK4103A]
MS0251-E-01 2009/01
- 5 -
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 3)
Parameter Symbol min max Units
Power Supply VDD -0.3 6.0 V
Input Current (All pins except supply pins) IIN -
±10
mA
Input Voltage VIND -0.3 VDD+0.3 V
Ambient Operating Temperature Ta -40 85
°C
Storage Temperature Tstg -65 150
°C
Note 3. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 3)
Parameter Symbol min typ max Units
Power Supply VDD 4.75 5.0 5.25 V
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
DC CHARACTERISTICS
(Ta=25°C; VDD=4.75~5.25V)
Parameter Symbol min typ max Units
Power Supply Current (fs=108kHz, Note 4) IDD 6 15 mA
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
2.4
-
-
-
-
0.8
V
V
High-Level Output Voltage
(Except TXP/N pins: Iout=-400µA)
(TXP/N pins: Iout= -8mA)
Low-Level Output Voltage
(Except TXP/N pins: Iout= 400µA)
(TXP/N pins: Iout= 8mA)
VOH
VOH
VOL
VOL
VDD-1.0
VDD-0.8
-
-
-
-
-
-
-
-
0.4
0.6
V
V
V
V
Input Leakage Current Iin - - ±10 μA
Note 4. Power supply current (IDD) is 3mA(typ)@fs=48kHz and 9mA(typ)@fs=192kHz.
IDD increases by 20mA(typ) with professional output driver circuit.
IDD is 350μA(typ) if PDN pin = “L”, TRANS pin = “H” and all other input pins except internal pull-up/pull-
down pins are held to VSS.
[AK4103A]
MS0251-E-01 2009/01
- 6 -
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75~5.25V; C
L
=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency
Duty Cycle
fCLK
dCLK
3.584
40
27.648
60
MHz
%
LRCK Timing
Frequency
Duty Cycle at Slave Mode
Duty Cycle at Master Mode
fs
dLCK
28
45
50
192
55
kHz
%
%
Audio Interface Timing
Slave Mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (
Note 5)
BICK “↑” to LRCK Edge (
Note 5)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
36
15
15
15
15
8
8
ns
ns
ns
ns
ns
ns
ns
Master Mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
SDTI Hold Time
SDTI Setup Time
fBCK
dBCK
tMBLR
tSDH
tSDS
-20
20
20
64fs
50
20
Hz
%
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z (
Note 6)
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
520
50
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-down & Reset Timing
PDN Pulse Width
tPDW
150
ns
Note 5. BICK rising edge must not occur at the same time as LRCK edge.
Note 6. CDTO pin is internally connected to a pull-down resistor.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

AK4103AVF

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IC TX DGTL AUD QD 192KHZ 24VSOP
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