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87952AYI-147LF

P1-P3P4-P6P7-P9P10-P12P13-P13
Low Skew, 1-to-11 LVCMOS/LVTTL
Clock Multiplier/Zero Delay Buffer
ICS87952I-147
DATA SHEET
ICS87952AYI-147 REVISION C AUGUST 4, 2009 1 ©2009 Integrated Device Technology, Inc.
BLOCK DIAGRAM PIN ASSIGNMENT
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
DDO
QA2
QA1
GNDO
QA0
V
DD
VDDA
nPLL_EN
V
DDO
QB2
QB3
GNDO
GNDO
QC0
QC1
V
DDO
VCO_SEL
F_SELC
F_SELB
F_SELA
MR/nOE
REF_CLK
GNDI
FB_IN
ICS87952I-147
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
PHASE
DETECTOR
nPLL_EN
REF_CLK
FB_IN
VCO_SEL
F_SELA
F_SELB
F_SELC
MR/nOE
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
GENERAL DESCRIPTION
The ICS87952I-147 is a low voltage, low skew
LVCMOS/LVTTL Clock Generator and a member of
the HiPerClockS™ family of High Performance Clock
Solutions from IDT. With output frequencies up to
180MHz, the ICS87952I-147 is targeted for high
performance clock applications. Along with a fully integrated PLL,
the ICS87952I-147 contains frequency configurable outputs and
an external feedback input for regenerating clocks with “zero de-
lay”.
For test and system debug purposes, the nPLL_EN input allows
the PLL to be bypassed. When HIGH, the MR/nOE input resets
the internal dividers and forces the outputs to the high impedance
state.
The low impedance LVCMOS/LVTTL outputs of the ICS87952I-
147 are designed to drive terminated transmission lines. The ef-
fective fanout of each output can be doubled by utilizing the abil-
ity of each output to drive two series terminated transmission lines.
FEATURES
• Fully integrated PLL
• Eleven LVCMOS / LVTTL outputs, 7Ω typical output impedance
• LVCMOS / LVTTL REF_CLK input
• Output frequency range up to 180MHz at V
DD
= 3.3V ± 5%
• VCO range: 240MHz - 480MHz
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 100ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
QC0
QC1
÷4/÷6
÷4/÷2
÷2/÷4
÷2
VCO
240 - 480MHz
LFP
GNDO
QB1
QB0
V
DDO
VDDO
QA4
QA3
GNDO
0
1
1
0
ICS87952AYI-147 REVISION C AUGUST 4, 2009 2 ©2009 Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep(
V
DD
V,
ODD
V564.3=52Fp
R
TUO
ecnadepmItuptuO 7
Ω
rebmuNemaNepyTnoitpircseD
1LES_OCVtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnitcelesOCV
2CLES_FtupnInwodlluP
.A
3elbaTnidebircsedsaCknaBrofseulavredividtuptuosenimreteD
.slevelecafretniLTTVL/SOMCVL
3BLES_FtupnInwodlluP
.A3elbaTnidebircsedsaBknaBrofseulavredividtuptuosenimreteD
.slevelecafretniLTTVL/SOMCVL
4ALES_FtupnInwodll
uP
.A3elbaTnidebircsedsaAknaBrofseulavredividtuptuosenimreteD
.slevelecafretniLTTVL/SOMCVL
5EOn/RMtupnInwodlluP
cigolnehW.elbanetuptuoWOLevitcA.teseRretsaMhgiHevitcA
.Z-iHnierastuptuoehtdnatesererasredividlanre
tnieht,HGIH
.delbaneerastuptuoehtdnasredividlanretnieht,WOLcigolnehW
.slevelecafretniLTTVL/SOMCVL.pu-re
wopnoderiuqertonteseR
6KLC_FERtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolcecnerefeR
7IDNGrewoP.dnuorgy
lppusrewoplanretnI
8NI_BFtupnInwodlluP
htiwskcolcgnitarenegrofrotcetedesahpottupnikcabdeeF
.slevelecafretni
LTTVL/SOMCVL."yaledorez"
9NE_LLPntupnInwodlluP
.LLPehtdnaKLC_FERneewtebstceleS.tupnitcelesLLP
.LLPstceles,W
OLnehW.KLC_FERstceles,HGIHnehW
.slevelecafretniLTTVL/SOMCVL
01V
ADD
rewoP.nipylppusgolanA
11V
DD
rewoP.nipylppuseroC
,41,21
91,81,51
,1AQ,0AQ
4AQ,3AQ,2AQ
tuptuO
7.stuptuokcolcAknaB Ω .ecnadepmituptuolacipyt
.
slevelecafretniLTTVL/SOMCVL
,71,31
92,82,42
ODNGrewoP.dnuorgylppusrewoptuptuO
,02,61
23,52,12
V
ODD
rewoP.snipylppustuptuO
,32,22
72,62
,1BQ,0BQ
3BQ,2BQ
tuptuO
7.stuptuokcolcBknaB Ω .ecnadepmituptuolacipyt
.slev
elecafretniLTTVL/SOMCVL
13,031CQ,0CQtuptuO
7.stuptuokcolcCknaB Ω .ecnadepmituptuolacipyt
.slevelecafretniLTT
VL/SOMCVL
:ETON
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 3A. F_SELX CONTROL INPUT FUNCTION T ABLE
tupnItuptuOtupnItuptuOtupnItuptuO
ALES_F4AQ:0AQBLES_F3BQ:0BQCLES_F1CQ:0CQ
04÷04÷02÷
16÷12÷14÷
tupnIlortnoC0cigoL1cigoL
LES_OCVOCVf2/OCVf
EOn/RMelbanEtuptuOecnadepmI-hgiH
NE_LLPnLLPelbanELLPelbasiD
TABLE 3B. VCO_SEL CONTROL SELECT FUNCTION T ABLE
ICS87952AYI-147 REVISION C AUGUST 4, 2009 3 ©2009 Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
FER
ycneuqerFecnerefeRtupnI
ybdetimilsiycneuqerfecnerefertupnI:ETON
.egnarkcolOCVehtdnanoitcelesredivideht
0
01zHM
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
egatloVylppuSgolanA 531.33.3564.3V
V
ODD
egatloVylppuStuptuO 531.33.3564.3V
I
DD
tnerruCylppuSrewoP 061Am
I
ADD
tnerruCylppuSgolanA 5102Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
DD
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tupnI
tnerruChgiH
,KLC_FER
,LES_OCV,NI_BF,EOn/RM
NE_LLPn,CLES_F:ALES_F
V
DD
V=
NI
V564.3=021Aµ
I
LI
tupnI
tnerruCwoL
,KLC_FER
,LES_OCV,NI_BF,EOn/RM
NE_LLPn,CLES_F:ALES_F
V
DD
V,V564.3=
NI
V0=021-Aµ
V
HO
egatloVhgiHtuptuOI
HO
Am02-=4.2V
V
LO
egatloVwoLtuptuOI
LO
Am02=5.0V
P1-P3P4-P6P7-P9P10-P12P13-P13

87952AYI-147LF

Mfr. #:
Buy 87952AYI-147LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 11 LVCMOS OUT CLOCK GENERATOR
Lifecycle:
New from this manufacturer.
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