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87952AYI-147LF

P1-P3P4-P6P7-P9P10-P12P13-P13
ICS87952AYI-147 REVISION C AUGUST 4, 2009 4 ©2009 Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 6. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
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f
XAM
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(BQ,CQ ÷ )2081zHM
(CQ,BQ,AQ ÷ )4021zHM
(AQ ÷ )608zHM
t
DP
NI_BFotKLC_FER,yaleDnoitagaporP
1ETON;)tesffOesahPcitatS(,yaleD
zHM05=KLC_FER001-002sp
f
OCV
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t
)o(ks
;wekStuptuO
3,2ETON
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knaBAQnihtiW 001sp
knaBBQnihtiW 001sp
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t
)cc(tij
;rettiJelcyC-ot-elcyC
3ETON
stuptuOllA
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upnI
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,zHM03=xCQ=xBQ
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,)6÷(1cigoL=ALES_F
,)4÷(0cigoL=BLES_F
)4÷(1cigoL=C
LES_F
052sp
t
)rep(tijrettiJdoirePstuptuOllA
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ycneuqerFemaS001sp
t
L
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t
R
t/
F
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t
ZLP
t,
ZHP
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t
LZP
emiTelbanEtuptuO 201sn
cdoelcyCytuDtuptuO 740535%
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ODD
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DD
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ODD
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ICS87952AYI-147 REVISION C AUGUST 4, 2009 5 ©2009 Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
GND
1.65V±5%
-1.65V±5%
CYCLE-TO-CYCLE JITTER
PERIOD JITTER
tsk(o)
V
DDO
2
V
DDO
2
OUTPUT SKEW
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
QAx,
QBx,
QCx
➤
➤
➤
➤
V
DDO
2
V
DDO
2
V
DDO
2
tcycle n tcycle n+1
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
t
PD
V
DD
2
V
DDO
2
FB_IN
REF_CLK
Qx
Qy
QAx,
QBx,
QCx
OUTPUT DUTY CYCLE/PULSE W IDTH/PERIOD
V
DD
,
V
DDO
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
Histogram
REF_CLK TO FB_IN DELAY
OUTPUT RISE/FALL TIME
0.8V
2V
2V
0.8V
t
R
t
F
QAx,
QBx,
QCx
ICS87952AYI-147 REVISION C AUGUST 4, 2009 6 ©2009 Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING T ECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS87952I-147 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be indi-
vidually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin.
Figure 1
illustrates this for a generic V
DD
pin and also shows that V
DDA
re-
quires that an additional10Ω resistor along with a 10µF bypass
capacitor be connected to the V
DDA
pin.
FIGURE 1. POWER SUPPLY FILTERING
V
DD
V
DDA
3.3V
10Ω
10µF.01µF
.01µF
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pulldowns; additional resistance is
not required but can be added for additional protection. A 1kΩ
resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left floating. There should be
no trace attached.
P1-P3P4-P6P7-P9P10-P12P13-P13

87952AYI-147LF

Mfr. #:
Buy 87952AYI-147LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 11 LVCMOS OUT CLOCK GENERATOR
Lifecycle:
New from this manufacturer.
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