ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8305AG REVISION C
MAY 30, 2014 7 ©2014 Integrated Device Technology, Inc.
Table 5C. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.15V, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at ƒ 350MHz unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using
the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 1.5V ± 5%, T
A
= 0°C to 70°C
For NOTES, see Table 5C above.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
tp
LH
Propagation
Delay,
Low to High
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
1.95 3.65 ns
tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 6 900 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
0.04 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 4 20% to 80% 100 700 ps
odc Output Duty Cycle
Ref = CLK/nCLK 44 56 %
Ref = LVCMOS_CLK, ƒ 300MHz 44 56 %
t
EN
Output Enable Time; NOTE 4 5ns
t
DIS
Output Disable Time; NOTE 4 5ns
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
tp
LH
Propagation
Delay,
Low to High
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
24ns
tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 6 1ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
0.04 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 4 20% to 80% 200 900 ps
odc Output Duty Cycle
ƒ 166MHz 45 55 %
ƒ > 166MHz 42 58 %
t
EN
Output Enable Time; NOTE 4 5ns
t
DIS
Output Disable Time; NOTE 4 5ns
