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74HC374D,653

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Nexperia
74HC374; 74HCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
74HC_HCT374 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 3 — 20 February 2018
7 / 17
10 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
T
amb
(°C)
25 -40 to +85 -40 to +125
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HC374
CP to Qn; see Figure 7
[1]
V
CC
= 2.0 V - 50 165 - 205 - 250 ns
V
CC
= 4.5 V - 18 33 - 41 - 50 ns
V
CC
= 5.0 V; C
L
= 15 pF - 15 - - - - - ns
t
pd
propagation
delay
V
CC
= 6.0 V - 14 28 - 35 - 43 ns
OE to Qn; see Figure 8
[2]
V
CC
= 2.0 V - 41 150 - 190 - 225 ns
V
CC
= 4.5 V - 15 30 - 38 - 45 ns
t
en
enable time
V
CC
= 6.0 V - 12 26 - 33 - 38 ns
OE to Qn; see Figure 8
[3]
V
CC
= 2.0 V - 50 150 - 190 - 225 ns
V
CC
= 4.5 V - 18 30 - 38 - 45 ns
t
dis
disable time
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
Qn; see Figure 7
[4]
V
CC
= 2.0 V - 14 60 - 75 - 90 ns
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
t
t
transition time
V
CC
= 6.0 V - 4 10 - 13 - 15 ns
CP; HIGH or LOW;
see Figure 7
V
CC
= 2.0 V 80 19 - 100 - 120 - ns
V
CC
= 4.5 V 16 7 - 20 - 24 - ns
t
W
pulse width
V
CC
= 6.0 V 14 6 - 17 - 20 - ns
Dn to CP; see Figure 7
V
CC
= 2.0 V 60 14 - 75 - 90 - ns
V
CC
= 4.5 V 12 5 - 15 - 18 - ns
t
su
set-up time
V
CC
= 6.0 V 10 4 - 13 - 15 - ns
Dn to CP; see Figure 7
V
CC
= 2.0 V 5 -6 - 5 - 5 - ns
V
CC
= 4.5 V 5 -2 - 5 - 5 - ns
t
h
hold time
V
CC
= 6.0 V 5 -2 - 5 - 5 - ns
Nexperia
74HC374; 74HCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
74HC_HCT374 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 3 — 20 February 2018
8 / 17
T
amb
(°C)
25 -40 to +85 -40 to +125
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
CP; see Figure 7
V
CC
= 2.0 V 6.0 23 - 4.8 - 4.0 - MHz
V
CC
= 4.5 V 30 70 - 24 - 20 - MHz
V
CC
= 5 V; C
L
= 15 pF - 77 - - - - - MHz
f
max
maximum
frequency
V
CC
= 6.0 V 35 83 - 28 - 24 - MHz
C
PD
power
dissipation
capacitance
per flip-flop; V
I
= GND to V
CC
[5]
- 17 - - - pF
74HCT374
CP to Qn; see Figure 7
[1]
V
CC
= 4.5 V - 16 32 - 40 - 48 ns
t
pd
propagation
delay
V
CC
= 5.0 V; C
L
= 15 pF - 13 - - - - - ns
t
en
enable time OE to Qn; V
CC
= 4.5 V;
see Figure 8
[2]
- 16 30 - 38 - 45 ns
t
dis
disable time OE to Qn; V
CC
= 4.5 V;
see Figure 8
[3]
- 18 28 - 35 - 42 ns
t
t
transition time Qn; V
CC
= 4.5 V; see Figure 7
[4]
- 5 12 - 15 - 18 ns
t
W
pulse width CP; HIGH or LOW;
V
CC
= 4.5 V; see Figure 7
19 11 - 24 - 29 - ns
t
su
set-up time Dn to CP; V
CC
= 4.5 V;
see Figure 7
12 7 - 15 - 18 - ns
t
h
hold time Dn to CP; V
CC
= 4.5 V;
see Figure 7
5 -3 - 5 - 5 - ns
CP; V
CC
= 4.5 V; see Figure 7 26 44 - 21 - 17 - MHzf
max
maximum
frequency
CP; V
CC
= 5 V; C
L
= 15 pF - 48 - - - - - MHz
C
PD
power
dissipation
capacitance
per flip-flop;
V
I
= GND to V
CC
- 1.5 V
[5]
- 17 - - - pF
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
en
is the same as t
PZH
and t
PZL
.
[3] t
dis
is the same as t
PHZ
and t
PLZ
.
[4] t
t
is the same as t
THL
and t
TLH
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in μW):
P
D
= C
PD
× V
CC
2
× f
i
× N + ∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs.
Nexperia
74HC374; 74HCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
74HC_HCT374 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 3 — 20 February 2018
9 / 17
10.1 Waveforms and test circuit
aaa-028160
Dn input
V
I
GND
CP input
V
I
GND
Qn output
V
OH
V
OL
t
h
t
PHL
t
PLH
t
h
t
su
t
su
1/f
max
t
THL
t
TLH
t
W
10 %
90 % 90 %
10 %
V
M
V
M
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Figure 7. Clock input (CP) to output (Qn) propagation delay, clock pulse width, data (Dn) to clock (CP) set-up and
hold times, output transition times (Qn) and maximum clock frequency
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Figure 8. 3-state enable and disable times
Table 8. Measurement points
Input OutputType
V
I
V
M
V
M
V
X
V
Y
74HC374 GND to V
CC
0.5 x V
CC
0.5 x V
CC
0.1 x V
CC
0.9 x V
CC
74HCT374 GND to 3 V 1.3 V 1.3 V 0.1 x V
CC
0.9 x V
CC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

74HC374D,653

Mfr. #:
Buy 74HC374D,653
Manufacturer:
Nexperia
Description:
Flip Flops OCTAL D F/F 3STATE
Lifecycle:
New from this manufacturer.
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