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MP18024HN-LF-Z

P1-P3P4-P6P7-P9P10-P12
MP18024
100V, 4A, High Frequency
Half-Bridge Gate Driver
MP18024 Rev. 1.0 www.MonolithicPower.com 1
6/3/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
The Future of Analog IC Technology
DESCRIPTION
The MP18024 is a high-frequency, 100V, half-
bridge, N-channel, power MOSFET driver. Its low-
side and high-side driver channels are
independently controlled and matched with less
than 5ns in time delay. Under-voltage lockout on
both high-side and low-side supplies force their
outputs low in case of insufficient supply. The
integrated bootstrap diode reduces external
component count.
FEATURES
Drives an N-Channel MOSFET Half Bridge
100V V
BST
Voltage Range
On-Chip Bootstrap Diode
Typical Propagation Delay of 20ns
Gate Drive Matching Of Less Than 5ns
Drives A 2.2nf Load with 15nm Rise Time
and 12ns Fall Time at12v VDD
TTL-Compatible Input
Quiescent Current of Less Than 150A
UVLO for Both High Side and Low Side
SOIC8E Package
APPLICATIONS
Telecom Half-Bridge Power Supplies
Avionics DC-DC Converters
Two-Switch Forward Converters
Active-Clamp Forward Converters
For MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks o
f
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP18024
PWM
CONTROLLER
INH
VSS
INL
DRVL
SW
DRVH
VDD
BST
+12V
48V
CONTROL
DRIVE
LO
DRIVE
HI
ISOLATION
AND
FEEDBACK
SECONDARY
SIDE
CIRCUIT
MP18024―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
MP18024 Rev. 1.0 www.MonolithicPower.com 2
6/3/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking
MP18024HN
SOIC8E
MP18024HN
* For Tape & Reel, add suffix –Z (e.g. MP18024HN–Z);
For RoHS compliant packaging, add suffix –LF; (e.g. MP18024HN–LF–Z)
PACKAGE REFERENCE
VDD
BST
DRVH
SW
DRVL
VSS
INL
INH
1
2
3
4
8
7
6
5
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage (V
DD
) ..................... -0.3V to +18V
SW Voltage (V
SW
) ....................... -5.0V to +105V
BST Voltage (V
BST
) ..................... -0.3V to +118V
BST to SW .................................... -0.3V to +18V
DRVH to SW ............. -0.3V to (BST-SW) + 0.3V
DRVL to VSS ................... -0.3V to (VDD + 0.3V)
All Other Pins ..................... -0.3V to (V
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= 25°C)
(2)
............................................................. 2.6W
Junction Temperature ............................... 150C
Lead Temperature .................................... 260C
Storage Temperature ............... -65°C to +150C
Recommended Operating Conditions
(3)
Supply Voltage V
DD
....................... 9.0V to 16.0V
SW Voltage (V
SW
) ......................... -1.0V to 100V
SW Slew Rate ....................................... <50V/ns
Operating Junction Temp. (T
J
) . -40C to +125C
Thermal Resistance
(4)
θ
JA
θ
JC
SOIC8E .................................. 48 ...... 10 ... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature T
J
(MAX), the junction-to-
ambient thermal resistance θ
JA
, and the ambient temperature
T
A
. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by P
D
(MAX)=(T
J
(MAX)-
T
A
)/ θ
JA
. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP18024―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
MP18024 Rev. 1.0 www.MonolithicPower.com 3
6/3/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
V
DD
= V
BST
-V
SW
= 12V, V
SS
= V
SW
= 0V, No load at DRVH and DRVL, T
A
= +25C, unless otherwise
noted.
Parameter Symbol Condition Min Typ Max Units
Supply Currents
VDD quiescent current I
DDQ
INL = INH = 0 100 150 µA
VDD operating current I
DDO
fsw = 500kHz 9 mA
Floating driver quiescent current I
BSTQ
INL = INH = 0 60 90 µA
Floating driver operating current I
BSTO
fsw = 500kHz 7.5 mA
Leakage current I
LK
BST = SW = 100V 0.05 1
A
Inputs
INL/INH High 2 2.4 V
INL/INH Low 1 1.4 V
INL/INH internal pull-down
resistance
R
IN
185
k
Under Voltage Protection
VDD rising threshold V
DDR
8.1 8.4 8.8 V
VDD hysteresis V
DDH
0.5 V
(BST-SW) rising threshold V
BSTR
6.9 7.3 7.7 V
(BST-SW) hysteresis V
BSTH
0.55 V
Bootstrap Diode
Bootstrap diode VF @ 100μA V
F1
0.5 V
Bootstrap diode VF @ 100mA V
F2
0.95 V
Bootstrap diode dynamic R R
D
@ 100mA 2
Low Side Gate Driver
Low level output voltage V
OLL
I
O
= 100mA 0.08 V
High level output voltage to rail V
OHL
I
O
= -100mA 0.23 V
Peak pull-up current I
OHL
V
DRVL
= 0V, V
DD
= 12V 3 A
V
DRVL
= 0V, V
DD
= 16V 4.7 A
Peak pull-down current I
OLL
V
DRVL
= V
DD
= 12V 4.5 A
V
DRVL
= V
DD
= 16V 6 A
Floating Gate Driver
Low level output voltage V
OLH
I
O
= 100mA 0.08 V
High level output voltage to rail V
OHH
I
O
= -100mA 0.23 V
Peak pull-up current I
OHH
V
DRVH
= 0V, V
DD
= 12V 2.6 A
V
DRVH
= 0V, V
DD
= 16V 4 A
Peak pull-down current I
OLH
V
DRVH
= V
DD
= 12V 4.5 A
V
DRVH
= V
DD
= 16V 5.9 A
P1-P3P4-P6P7-P9P10-P12

MP18024HN-LF-Z

Mfr. #:
Buy MP18024HN-LF-Z
Manufacturer:
Monolithic Power Systems (MPS)
Description:
Gate Drivers 4A 100V High f Half-Bridge Gate Drv
Lifecycle:
New from this manufacturer.
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