MP18024―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
MP18024 Rev. 1.0 www.MonolithicPower.com 4
6/3/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= V
BST
-V
SW
= 12V, V
SS
= V
SW
= 0V, No load at DRVH and DRVL, T
A
= 25C, unless otherwise
noted.
Parameter Symbol Condition Min Typ Max Units
Switching Spec. --- Low Side Gate Driver
Turn-off propagation delay
INL falling to DRVL falling
T
DLFF
20 ns
Turn-on propagation delay
INL rising to DRVL rising
T
DLRR
20
DRVL rise time C
L
= 2.2nF 15 ns
DRVL fall time C
L
= 2.2nF 9 ns
Switching Spec. --- Floating Gate Driver
Turn-off propagation delay
INL falling to DRVH falling
T
DHFF
20 ns
Turn-on propagation delay
INL rising to DRVH rising
T
DHRR
20 ns
DRVH rise time C
L
= 2.2nF 15 ns
DRVH fall time C
L
= 2.2nF 12 ns
Switching Spec. --- Matching
Floating driver turn-off to low
side drive turn-on
T
MON
1 5 ns
Low side driver turn-off to floating
driver turn-on
T
MOFF
1 5 ns
Minimum input pulse width that
changes the output
T
PW
50
(5)
ns
Bootstrap diode turn-on or turn-
off time
T
BS
10
(5)
ns
Thermal shutdown 150
C
Thermal shutdown hysteresis 25
C
Note:
5) Guaranteed by design.
INPUT
(INH, INL)
OUTPUT
(DRVH,
DRVL)
T
DHRR
, T
DLRR
T
DHFF
, T
DLFF
INPUT
(INH, INL)
OUTPUT
(DRVH,
DRVL)
T
DHRR
, T
DLRR
T
DHFF
, T
DLFF
INL
INH
DRVL
DRVH
T
MON
T
MOFF
Figure 1—Timing Diagram