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AD5206BRUZ10

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD5204/AD5206 Data Sheet
Rev. D | Page 16 of 20
TEST CIRCUITS
340kΩ
V
SS
LOGIC
06884-050
Figure 25. ESD Protection of Digital Pins
A, B, W
06884-051
V
SS
Figure 26. ESD Protection of Resistor Terminals
V+
DUT
V
MS
A
B
W
V+ = V
DD
1LSB = V+/256
06884-036
Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
DUT
V
MS
A
B
W
NO CONNECT
I
W
06884-037
Figure 28. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
V+
A
B
W
DUT
I
MS
V
MS
I
W
=
1V/R
NOMINAL
I
W
V
W
V+ V
DD
R
W
=
WHERE V
W1
= V
MS
WHEN I
W
= 0
AND V
W2
= V
MS
WHEN I
W
= 1/R
V
W2
– [V
W1
+ I
W
(R
AW
II R
BW
)]
0
6884-052
Figure 29. Wiper Resistance Test Circuit
V+
A
B
W
~
V
A
V
MS
V
DD
V+ = V
DD
± 10%
PSRR (dB) = 20 log
∆V
MS
∆V
DD
PSS (%/%) =
∆V
MS
%
∆V
DD
%
( )
0
6884-039
Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)
A
V
IN
OFFSET BIAS
OP279
5V
V
OUT
DUT
W
OFFSET
GND
B
0
6884-040
Figure 31. Inverting Programmable Gain Test Circuit
A
V
IN
OFFSET BIAS
OP279
5
V
V
OUT
DUT
W
OFFSET
GND
B
06884-041
Figure 32. Noninverting Programmable Gain Test Circuit
B
A
V
IN
2.5V
+15V
V
OUT
DUT
W
–15V
FFSET
GND
OP42
0
6884-042
Figure 33. Gain vs. Frequency Test Circuit
DUT
I
SW
B
W
V
SS
TO V
DD
R
SW
=
0.1
V
I
SW
CODE =
0x00
0.1V
+
–
06884-043
Figure 34. Incremental On-Resistance Test Circuit
Data Sheet AD5204/AD5206
Rev. D | Page 17 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001
071006-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
24
1
12
13
0.100 (2.54)
BSC
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0
.
7
5
(
0
.
0
2
9
5
)
0
.
2
5
(
0
.
0
0
9
8
)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
24
13
12
1
1.27 (0.0500)
BSC
12-09-2010-A
Figure 36. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
AD5204/AD5206 Data Sheet
Rev. D | Page 18 of 20
24
13
121
6.40 BSC
4.50
4.40
4.30
PIN 1
7.90
7.80
7.70
0.15
0.05
0.30
0.19
0.65
BSC
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 37. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
3.45
3.30 SQ
3.15
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
1
32
8
9
25
24
17
16
COPLANARITY
0.08
3.50 REF
0.50
BSC
PIN 1
INDICATOR
PIN 1
INDICATOR
0.30
0.25
0.18
0.20 REF
12° MAX
0.80 MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.50
0.40
0.30
5.00
BSC SQ
4.75
BSC SQ
0.60 MAX
0.60 MAX
0.25 MIN
05-23-2012-A
TOP VIEW
EXPOSED
PAD
BOTTOM VIEW
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1, 2
kΩ Temperature Range Package Description Package Option
AD5204BR10 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
AD5204BRZ10 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
AD5204BRZ10-REEL 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
AD5204BRUZ10 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5204BRUZ10-REEL7 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5204BCPZ10-REEL 10 −40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3
AD5204BCPZ10-REEL7 10 −40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3
AD5204BRZ50-REEL 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
AD5204BRUZ50 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5204BRUZ50-REEL7 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5204BRZ100 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
AD5204BRUZ100 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5204BRUZ100-R7 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5206BRUZ10

Mfr. #:
Buy AD5206BRUZ10
Manufacturer:
Analog Devices Inc.
Description:
Digital Potentiometer ICs IC 6-CH8Bit
Lifecycle:
New from this manufacturer.
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