AD5204/AD5206 Data Sheet
Rev. D | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
INTERFACE TIMING CHARACTERISTICS
7, 11, 12
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 20 ns
Data Setup Time t
DS
5 ns
Data Hold Time t
DH
5 ns
CLK-to-SDO Propagation Delay
13
t
PD
R
L
= 2 kΩ , C
L
< 20 pF 1 150 ns
CS Setup Time
t
CSS
15 ns
CS High Pulse Width
t
CSW
40 ns
Reset Pulse Width t
RS
90 ns
CLK Fall to CS Fall Setup
t
CSH0
0 ns
CLK Fall to CS Rise Hold Time
t
CSH1
0 ns
CS Rise to Clock Rise Setup
t
CS1
10 ns
1
Typicals represent average readings at 25°C and V
DD
= 5 V.
2
Applies to all VRs.
3
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.
I
W
= V
DD
/R for both V
DD
= 3 V and V
DD
= 5 V.
4
V
AB
= V
DD
, wiper (V
W
) = no connect.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27.
6
Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.
7
Guaranteed by design and not subject to production test.
8
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= 5 V.
11
Applies to all parts.
12
See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V
DD
= 3 V and V
DD
= 5 V.
13
The propagation delay depends on the values of V
DD
, R
L
, and C
L
(see the Operation section).
Data Sheet AD5204/AD5206
Rev. D | Page 5 of 20
TIMING DIAGRAMS
06884-003
SDI
CLK
V
OUT
CS
1
0
1
0
1
0
V
DD
0V
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
RDAC LATCH LOAD
Figure 3. Timing Diagram
SDI
(DATA IN)
SDO
(DATA OUT)
1
0
1
0
1
0
1
0
V
DD
0V
CLK
CS
V
OUT
Ax OR Dx Ax OR Dx
Ax OR Dx Ax OR Dx
t
CSS
t
DH
t
PD_MAX
t
CSH0
±1 LSB ERROR BAND
±1 LSB
t
CSH1
t
CH
t
CSW
t
S
t
CL
t
DS
t
CS1
06884-004
Figure 4. Detailed Timing Diagram
±1 LSB
±1 LSB ERROR BAND
1
0
V
DD
0V
V
OUT
t
RS
t
S
PR
06884-005
Figure 5. AD5204 Preset Timing Diagram
AD5204/AD5206 Data Sheet
Rev. D | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 2.
Parameter Rating
V
DD
to GND −0.3 V to +7 V
V
SS
to GND 0 V to −7 V
V
DD
to V
SS
7 V
V
A
, V
B
, V
W
to GND V
SS
, V
DD
I
A
, I
B
, I
W
Pulsed
1
±20 mA
Continuous
10 kΩ End-to-End Resistance
±11 mA
50 kΩ and 100 kΩ End-to-End
Resistance
±2.5 mA
Digital Input and Output Voltage
to GND
−0.3 V to (V
DD
+ 0.3 V) or 7 V
(whichever is less)
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature
(T
J
max)
150°C
Storage Temperature −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (T
J
max − T
A
)/θ
JA
Thermal Resistance, θ
JA
2
PDIP (N-24-1) 63°C/W
SOIC (RW-24) 52°C/W
TSSOP (RU-24) 50°C/W
LFCSP (CP-32-3) 32.5°C/W
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Thermal resistance (JEDEC 4-layer (2S2P) board). Paddle soldered to board.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION

AD5206BRUZ10

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Potentiometer ICs IC 6-CH8Bit
Lifecycle:
New from this manufacturer.
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