ADG752
–6–
FREQUENCY – MHz
100
ATTENUATION – dB
101
–8
–4
–2
0
–6
T
A
= +258C
Figure 7. On Response vs. Frequency
GENERAL DESCRIPTION
The ADG752 is an SPDT switch constructed using switches in
a T configuration to obtain high “OFF” isolation while main-
taining good frequency response in the “ON” condition.
Figure 8 shows the T-switch configuration. While the switch is
in the OFF state, the shunt switch is closed and the two series
switches are open. The closed shunt switch provides a signal
path to ground for any of the unwanted signals that find their
way through the off capacitances of the series’ MOS devices.
This results in more improved isolation between the input and
output than with an ordinary series switch. When the switch is
in the ON condition, the shunt switch is open and the signal
path is through the two series switches which are now closed.
D
IN
S
SERIES
SHUNT
Figure 8. Basic T-Switch Configuration
LAYOUT CONSIDERATIONS
Where accurate high frequency operation is important, careful
consideration should be given to the printed circuit board layout
and to grounding. Wire wrap boards, prototype boards and
sockets are not recommended because of their high parasitic
inductance and capacitance. The part should be soldered di-
rectly to a printed circuit board. A ground plane should cover all
unused areas of the component side of the board to provide a
low impedance path to ground. Removing the ground planes
from the area around the part reduces stray capacitance.
Good decoupling is important in achieving optimum perfor-
mance. V
DD
should be decoupled with a 0.1 µF surface mount
capacitor to ground mounted as close as possible to the device
itself.
V
DD
IN
ADG752
D
S1
S2
75V
V
OUT
75V
CH1
CH2
A
=
2
250V
250V
75V
75V
Figure 9. Multiplexing Between Two Video Signals
REV. A
ADG752
–7–
V
S
V
OUT
50V
NETWORK
ANALYZER
R
L
50V
IN
GND
V
DD
V
DD
V
IN
S
0.1mF
D
INSERTION LOSS = 20 LOG
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
Test Circuit 8. Bandwidth
SD
V
S
R
ON
= V1/I
DS
I
DS
V1
Test Circuit 1. On Resistance
SD
V
S
A
V
D
I
S
(OFF)
Test Circuit 2. Off Leakage
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
Test Circuit 3. On Leakage
Test Circuits
CHANNEL-TO-CHANNEL
CROSSTALK = 20 LOG
GND
V
DD
0.1mF
V
DD
S1
D
S2
V
S
V
OUT
NETWORK
ANALYZER
R
L
50V
IN
V
OUT
V
S
50V
Test Circuit 7. Channel-to-Channel Crosstalk
V
S
V
OUT
50V
NETWORK
ANALYZER
R
L
50V
IN
GND
V
DD
V
DD
V
IN
S
0.1mF
D
50V
OFF ISOLATION = 20 LOG
V
OUT
V
S
Test Circuit 6. Off Isolation
50%
50%
50%
50%
t
D
t
D
0V
0V
V
OUT
V
IN
IN
GND
R
L
300V
C
L
35pF
V
OUT
V
DD
0.1mF
V
DD
S1
D
S2
V
S
D2
V
IN
Test Circuit 5. Break-Before-Make Time Delay, t
D
V
S
IN
GND
R
L
300V
C
L
35pF
V
OUT
V
DD
0.1mF
V
DD
S1
D
S2
90%
90%
50% 50%V
IN
V
OUT
t
OFF
t
ON
GND
V
S
Test Circuit 4. Switching Times
REV. A
ADG752
Rev. A | Page 8
OUTLINE DIMENSIONS
Figure 10. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Figure 11. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
COMPLIANT TO JEDEC STANDARDS MO-178-AB
10°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
65
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.30 MIN
0.55
0.45
0.35
PIN 1
INDICATOR
12-16-2008-A

ADG752BRMZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 80dB 150 Ohm 250MHz CMOS RF/Video SPDT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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