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MC100EP16VSDT

P1-P3P4-P6P7-P9P10-P12
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 6
1 Publication Order Number:
MC100EP16VS/D
MC100EP16VS
3.3V / 5V ECL Differential
Receiver/Driver with
Variable Output Swing
Description
The MC100EP16VS is a differential receiver with variable output
amplitude. The device is functionally equivalent to the 100EP16 with
an input pin that controls the amplitude of the outputs.
The V
CTRL
input pin controls the output amplitude of the EP16VS
and is referenced to V
CC
. (See Figure 4.) The operational range of the
V
CTRL
input is from ≤ V
BB
(max output amplitude) to V
CC
(min
output amplitude). (See Figure 3.) A variable resistor between the V
CC
and V
BB
pins, with the wiper driving V
CTRL
, can control the output
amplitude. Typical application circuits and a V
CTRL
Voltage vs.
Output Amplitude graph are described in this data sheet. When left
open, the V
CTRL
pin will be internally pulled down to V
EE
and operate
as a standard EP16, with 100% output amplitude.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
• 220 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical (See Graph)
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V
EE
• Pb−Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
ALYWG
G
KP62
MARKING
DIAGRAMS*
SOIC−8
D SUFFIX
CASE 751
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
1
8
KEP62
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
3H MG
G
14
(Note: Microdot may be in either location)
MC100EP16VS
http://onsemi.com
2
1
2
3
45
6
7
8
Q
V
EE
V
CC
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
D
Q
D
V
BB
V
CTRL
D*, D** ECL Data Inputs
Q, Q
ECL Data Outputs
V
CTRL
* Output Swing Control
V
BB
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
NC No Connect
Table 1. PIN DESCRIPTION
* Pins will default LOW when left open.
** Pins will default to V
CC
/2 when left open.
PIN FUNCTION
2, 3
6, 7
1
4
8
5
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND)
or leave unconnected, floating open.
EP
−
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
SOIC−8
TSSOP−8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 140 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EP16VS
http://onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6
−6
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder Pb
Pb−Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
P1-P3P4-P6P7-P9P10-P12

MC100EP16VSDT

Mfr. #:
Buy MC100EP16VSDT
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 3.3V/5V ECL Diff
Lifecycle:
New from this manufacturer.
Delivery:
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