XRD98L59
12
Rev. 2.00
CORRELATED DOUBLE SAMPLE/HOLD (CDS)
The function of the CDS block is to sense the voltage
difference between the black level and video level for
each pixel. The PGA then amplifies this difference to the
desired level for the ADC. The CDS and PGA are fully
differential. The PGA output is converted to a single
ended signal and fed to the ADC. The CCDin pin (CDS
inverting input) should be connected, via a capacitor, to
the CCD output signal. The REFin pin (CDS non-
inverting input) should be connected, via a capacitor, to
the CCD “Common” voltage. This is typically the CCD
Reference output or ground.
At the beginning (or end) of every video line, the DC
restore switch forces one side of the external capacitors
to an internal Vbias1 level (approximately 0.8V). The DC
restore switch is controlled by the combination of the
CLAMP signal ANDed with the φ2 clock. (See Figure 5).
During the black reference phase of each CCD pixel the
φ1 (Sample Black Reference) switches are turned on,
shorting the PGA1 inputs to a second bias level. The
Coarse Offset DAC adds an adjustment to the Vbias2
level to cancel offset in the CCD signal. When the φ1
switches turn off, the pixel black reference(V
BLACK
) is
sampled on the internal reference sample capacitors,
and the PGA is ready to gain up the CCD video signal.
During the video phase of each CCD pixel the difference
between the pixel black reference level and video level is
transmitted through the internal reference sample ca-
pacitors and converted to a fully differential signal by the
PGA1 amplifier. At this time the φ2 (Sample Pixel value)
switches turn on, and the internal video sample capaci-
tors track the amplified difference.
Figure 5. Block Diagram of CDS and PGAs
φ
1
CLAMP
Vbias1~0.8V
Vbias2
REFin
CCDin
PGA1 PGA2
CCD
Coarse
Offset
DAC
PGACDS
External
DC blockin
capacitors
Internal
black sample
capacitors
~5PF
Reset re
ect
switches
Internal
video sample
DC restore
switches
Fine
Offset
DAC
AGND
To ADC
XRD98L59
φ
2
φ
2
capacitors
~5PF
r
ON
120
Ω
