OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

XRD98L59AIG-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
19
Rev. 2.00
XRD98L59
Figure 12. Example of CLAMP & CAL Line Calibration Mode Timing
(CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 0001 0011
Line N Line N+1
* Note: OB = Optically Black or Shielded pixels.
Active Video
pixels
OB* pixels
Vertical Shift
Dummy &
OB* pixels
CAL
CLAMP
CCD Signal
Active Video
pixels
(Horizontal Clocking
Off)
Min 1 Pixel
Min 1 Pixel
Line Timing: CAL Only
CAL Only Line Timing
(SDI address = 0011, D4 = 0)
The timing needed for "CAL Only" Line Calibration Mode
is shown in Figure 13. In "CAL Only" Line Calibration the
timing signal CAL has two functions, DC Clamping of the
CCDIN and REFin inputs and gating the auto-calibration
logic. Using "CAL Only" Line Timing enables the de-
signer to eliminate the requirement of providing a
CLAMP Timing signal to the XRD98L59.
XRD98L59
20
Rev. 2.00
Most timing generators (TG’s) define the start of line and
end of line OB pixels on the CCD array. The CAL timing
signal should always be active for the greatest number of
OB pixels possible, either during start or end of line. The
more OB pixels that the XRD98L59 can use for its auto-
calibration, the faster it can achieve and maintain calibra-
tion.
While in “CAL ONLY” Line Calibration Timing Mode,
CLAMP needs to be held inactive during the output of
active video and OB pixels from the CCD. Figure 13
shows the minimum timing requirements for the “CAL
ONLY” Line Calibration Timing Mode. The inactive
state for CLAMP depends on the CLAMP-Polarity
setting (Clock Reg bit D1).
End of Line N
Start of Line N+1
Active Video
Pixels
OB Pixels Vertical Shift
Dummy &
OB Pixels
CAL
Internal
DC Restore Time
CCD
Si
g
nal
Active Video Pixels
t
CAL
(min 5 Pixels)
4 Pixels
(D1 = 0)
CLAMP
Internal Black Level
Calibration Time
t
CAL
- 4 Pixels
Figure 13. Example of Minimum Timing Requirements for CAL Only Line Calibration Mode
(CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 0000 0000
Vertical Shift Reject
The CLAMP input can be used to implement a Vertical
Shift Reject function while in “CAL ONLY” Line Cali-
bration Timing Mode. The Vertical Shift Rejection,
also called preblanking, can be used to reject and any
large transients present in the CCD output during the
vertical clocking.
To implement the Vertical Shift Reject (Preblanking)
function on the XRD98L59 the CLAMP opt bit must be
low (Clock Reg D4=0) and the CLAMP input driven
with the preblanking timing signal. The preblanking
timing signal, commonly called PBLK, is generated by
the system timing generator and defines the vertical
shift of the CCD (see Figure 13a). The preblanking
pulse opens the Reset Reject Switches internal to the
XRD98L59, see Figure 5, thereby rejecting any
transients in the CCD output while the vertical shifting
is being done.
21
Rev. 2.00
XRD98L59
End of Line N
Start of Line N+1
Active Video
Pixels
OB Pixels Vertical Shift
Dummy &
OB Pixels
CAL
Internal
DC Restore Time
CCD
Si
g
nal
Active Video Pixels
t
CAL
(min 5 Pixels)
4 Pixels
(D1 = 0)
CLAMP
Internal Black Level
Calibration Time
t
CAL
- 4 Pixels
Figure 13a. Example of Vertical Shift Reject Timing using the CLAMP input while in “CAL ONLY”
Line Calibration Mode. (CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 000 0000
÷
ø
ö
ç
è
æ
´+= 32
256
6][
Code
dBGain
PROGRAMMABLE GAIN AMPLIFIER (PGA)
PGA1 provides gains of 0dB, 8dB & 16dB (1x, 2.5x, and
6.25x). The gain transitions occur at PGA gain codes 64d
and 128d (40h & 80h). PGA2 provides gain from 6dB to
22dB (2x to 12.5x) with 0.125dB steps. The combined
PGA blocks provide a programmable gain range of 32dB.
The minimum gain (code 00h) is 6dB. The maximum gain
(code FFh) is 38dB. The following equation can be used
to compute PGA gain from the gain code:
where
Code
is the 8 bit value (0 to 255) programmed in
the serial interface Gain register. Due to device
mismatch the gain steps at codes 63 - 64 and 127 -
128 may not be monotonic.
ANALOG TO DIGITAL CONVERTER (ADC)
The analog-to-digital converter is based upon a two-step
sub-ranging flash converter architecture with a built in
track and hold input stage. The ADC conversion is
controlled by an internally generated signal, ADCLK (see
Figure 10). The ADC tracks the output of the PGA while
ADCLK is high and holds when ADCLK is low. This allows
maximum time for the PGA output to settle to its final
value before being sampled. The conversion is then
performed and the parallel output is updated, after a 2.5
cycle pipeline delay, on the edge of φ2. The pipeline delay
of the entire XRD98L59 is 4 clock cycles.
The ADC reference levels, VRT & VRB, are set by an
internal resistor divider between VDD and GND. The
divider provides VRB=VDD/10 and VRT=VDD/1.3. To
maximize the performance of the XRD98L59, VRT &
VRB should have high frequency by-pass capacitors to
AGND. The value of these by-pass capacitors will affect
the time required for the reference to charge up and settle
after power down mode. Using 0.01uF capacitors will
give about 40 µs settling time for full accuracy.
The ADC output bus is equipped with a high impedance
capability which is controlled by OE bit in the serial
interface control register. The outputs are enabled when
the OE bit is high, and go into high impedance mode when
the OE bit is low.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

XRD98L59AIG-F

Mfr. #:
Buy XRD98L59AIG-F
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet