LT3965/LT3965-1
10
39651fa
For more information www.linear.com/LT3965
APPLICATIONS INFORMATION
OVERVIEW
The LT3965/LT3965-1 is an 8-channel LED bypass switch-
ing device
with I
2
C serial interface, designed for dimming
LED strings using a common current source. Each of
the eight channels can be independently programmed to
bypass the LED string in constant on or off, or dimming
with or without fade transition. Operation can be best
understood by referring to the block diagram in Figure 1.
The LT3965/LT3965-1 operates over the V
DD
input sup-
ply range of 2.7V to 5.5V. The eight channel switches are
powered
by the V
IN
input supply and can be connected in
parallel and/or in series. Each of the eight channel switches
can bypass one or more LEDs up to 17V in a string.
Each channel has an LED fault detector which can be pro
-
grammed to detect
an open LED fault at one of the four
threshold levels: 4.5V, 9V (default setting of LT3965-1),
13.5V and 18V (default setting of LT3965). If EN/UVLO is
high, when an open LED fault is detected in a channel, the
channel switch will be turned on to bypass the faulty LED to
maintain the continuity of the string and for
self protection
.
The PWM dimming for this channel is interrupted until reset
by the serial interface. With a proper LED reference voltage
(<4V) applied to the LEDREF pin, each channel LED fault
detector can be programmed to detect a single-shorted LED
fault (default setting), a 2-shorted LED fault, a 3-shorted LED
fault or a 4-shorted LED fault in a multi-LED segment. When
a shorted LED fault is detected in a channel, the channel
switch will continue with the programmed PWM dimming.
Besides LED faults, the LT3965/LT3965-1 also detects and
reports an overheat fault condition (≥170°C). The LT3965/
LT3965-1 asserts (pulls down) the ALERT pin to interrupt
the bus master when an LED fault and/or an overheat fault
is detected. The master can use the alert response address
(ARA) to determine which device is sending the alert.
The LT3965/LT3965-1 I
2
C serial interface contains nine
command registers for configuring channel switches and
LED fault detectors. It also contains two read-only fault
status registers for reporting the LED and overheat faults.
The I
2
C serial interface supports random addressing of
any register. The LT3965/LT3965-1 address select pins
ADDR4, ADDR3, ADDR
2 and ADDR1
allow up to 16 LT3965/
LT3965-1 devices to share the I
2
C bus.
If a resistor is connected between the RTCLK pin and the
ground, the internal oscillator is chosen and the LED dimming
frequency is set by the resistor. If the RTCLK pin is driven by
an external clock source, the external clock source is used to
override the internal oscillator and the dimming frequency
equals the external clock frequency divided by 2048.
DIFFERENCES BETWEEN LT3965 AND LT3965-1
The LT3965 and the LT3965-1 have different default
command register values, which result in different initial
switch states and different open LED threshold settings after
POR (Power On Reset). Otherwise they are the same (see
Table 1 and Table 2 for default register values).
Details of the LT3965/LT3965-1 operation are found in
the following sections.
EN/UVLO SHUTDOWN
The EN/UVLO pin resets the internal logic and controls
whether the LT3965/LT3965-1 is enabled or is in shutdown
state. The LT3965/LT3965-1 indicates that the part is in
shutdown state by setting all OLFREG and SLFREG register
bits high and deasserting the ALERT pin. In the shutdown
state, the serial interface is alive as long as
V
DD
is applied.
Any data written while EN/UVLO is low will be reset when it
transitions high. The eight channel switches are off and the
alert function is disabled in shutdown condition. Because
V
IN
must be at least 7.1V higher than the channel source
voltage for proper channel switch bypass operation, it is
recommended to enable the IC when V
IN
is at least 7.1V
higher than V
LED
+
. The PNP based level shifter shown in
Figure 1 can be used to generate EN/UVLO input signal. A
micropower 1.24V reference, a comparator and controllable
current source, I
S1
, allow the user to accurately program
the V
IN
V
LED
+
voltage at which the IC turns on and off
(see Figure 1). When EN/UVLO is above 0.7V, and below
the 1.24V threshold, the small pull-down current source,
I
S1
, (typical 2.7μA) is active. The purpose of this current
is to allow the user to program the rising hysteresis.
The typical falling threshold voltage and rising threshold
voltage can be calculated by the following equations:
(
V
IN
V
LED
+
)
(FALLING)
=1.24
R1
R2
+ V
BE
(
V
IN
V
LED
+
)
(RISING)
= 2.7µA R1+(V
IN
V
LED
+
)
(FALLING)
LT3965/LT3965-1
11
39651fa
For more information www.linear.com/LT3965
APPLICATIONS INFORMATION
POR
1/256 DIMMING (8 CLOCK CYCLES)
PHASE SHIFT OF 1/8 DIMMING CYCLE = 256 CLOCK CYCLES
1 DIMMING CYCLE = 2048 RTCLK CLOCK CYCLES
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
3965 F02
Figure 2. POR Dimming Cycle Initialization Diagram
Typically V
BE
is 0.6V. The recommended value of R1 is 49.9k
and therefore the rising hysteresis is 0.14V. Then the value
of R2 can be chosen to ensure that (V
IN
V
LED
+
)
(FALLING)
is greater than 7.1V when the part is enabled.
POWER-ON RESET AND DIMMING CYCLE
INITIALIZATION
When the EN/UVLO pin is toggled high, an internal power-
on reset (POR) signal is generated to set all registers to
their default states. The eight channel switches are in off
state (all channel LEDs are on) upon the POR. The POR
also initializes each channel’s PWM dimming counter with
one-eighth dimming cycle shift, which can avoid simul
-
taneous channel
switching at the beginning of dimming
cycle to reduce switching transients (see Figure 2). When
in PWM dimming mode (with or without fade transition),
the channel LED string is always being turned on at the
beginning of its dimming cycle. The channel LED string
will be turned off if the value of the channel counter, which
is clocked by the internal oscillator or an external clock
source, equals the dimming value stored in the channel
SCMREG command register. Once the channel LED
string is
t
urned off, it remains off until its next dimming cycle starts.
DIMMING WITHOUT FADE TRANSITION VS DIMMING
WITH FADE TRANSITION
Each channel of the LT3965/LT3965-1 can be independently
programmed to perform dimming without fade transition
or dimming with fade transition. For dimming without fade
transition, the dimming changes from the initial value to
the target value in one dimming cycle. For dimming with
fade transition, the dimming changes transitionally from
the initial value to the target value step by step in multiple
dimming cycles, following a predetermined logarithmic
curve, which can favor the approximately logarithmic re
-
sponse of the human eye to brightness. The initial value is
an
existing 8-bit dimming value stored in channel SCMREG
register. The target value comes from a SCMODE long
format write command and will be stored in the register
to replace the initial value when the STOP condition is
received. For dimming with fade transition, each transi
-
tional step value is calculated using 11 bits according to
the following formula: DV
NEXT
= DV
PRESENT
CF, where
DV represents a transitional step dimming value, CF is a
constant factor. CF is 1.0625 for up transition and 0.9375
for down transition. The transition process begins with
the initial value served as the first DV
PRESENT
, and ends
with the target value when the last DV
NEXT
is no less than
the target value in up transition or no more than the target
value in down transition.
The number of the transitional steps depends on the
distance between the initial value and the target value.
The maximum number of transitional steps from 1(/256)
dimming to 255(/256) dimming is 100 (see Figure 3) and
the maximum number of transitional steps from 255(/256)
dimming to 1(/256) dimming is 92 (see Figure 4). Each
step runs 4 PWM dimming cycles, and each dimming
cycle consists of 2048 RTCLK clock cycles. Then T
STEP
=
T
PWM
• 4 = T
RTCLK
• 8192
LT3965/LT3965-1
12
39651fa
For more information www.linear.com/LT3965
APPLICATIONS INFORMATION
LT3965/LT3965-1 I
2
C REGISTERS
The LT3965/LT3965-1 has nine command registers (see
Table 1 and Table 2) and two read-only fault status registers
(see Table3). The command registers are used to store
the configuration bits sent by a master. The fault status
registers are used to store the LED/overheat fault status
bits. Both the command registers and the fault status
registers can be read by the master.
LT3965/LT3965-1 COMMAND REGISTERS AND
CHANNEL CONTROL
Upon the POR with EN/UVLO, all eight channel switches of
LT3965 are set to off, whereas all eight channel switches of
LT3965-1 are set to on, which is controlled by the ACMREG
register default value ("11111111" for LT3965; "00000000"
for LT3965-1). After data is written, each channel switch
is controlled either by the ACMODE register or by the
channel SCMREG register, depending on which register
has been last updated (see Figure 5). If SCMODE registers
are dominant, the data in the ACMODE register is retained
until it is overwritten or a POR occurs.
I
2
C SERIAL INTERFACE
The LT3965/LT3965-1 communicates through an I
2
C serial
interface. The I
2
C serial interface is a 2-wire open-drain
interface supporting multiple slaves and multiple masters
on
a single bus. Each device on the I
2
C bus is recognized
by a unique address stored in the device and can only
operate either as a transmitter or receiver, depending on
the function of the device. A master is the device which
initiates a data transfer on the bus and generates the clock
signals to permit the transfer. Devices addressed by the
master are considered slaves. The LT3965/LT3965-1 can
only be addressed as a slave. Once addressed, it can receive
configuration data or transmit register contents. The serial
clock line (SCL) is always an input to the LT3965/LT3965-1
and the serial data line (SDA) is bidirectional. The LT3965/
LT3965-1 can only pull the serial data line (SDA) LOW and
can never drive it HIGH. SCL and SDA are required to be
externally connected to the V
DD
supply through a pull-up
resistor. When the data line is not being driven LOW, it is
HIGH. Data on the I
2
C bus can be transferred at rates up
to 100kbits/s in the standard mode and up to 400kbits/s
in the fast mode.
THE START AND STOP CONDITIONS
When
the bus is idle, both SCL and SDA must be HIGH. A
bus
master signals the beginning of a transmission with a
START condition by transitioning SDA from HIGH to LOW
while SCL is HIGH. When the master has finished com
-
municating with
the slave, it issues a STOP condition by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is then free for another transmission. However,
if the master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and ad
-
dress the
same or another slave without first generating
a
STOP condition. When the bus is in use, it stays busy
if a repeated START (Sr) is generated instead of a STOP
NUMBER OF STEPS
0
DIMMING VALUE (255 TO 1)
96
128
160
60
100
3865 F04
64
32
0
20 40 80
192
224
256
PWM DIMMING (99.6% TO 0.4%)
37.5%
50.0%
62.5%
25.0%
12.5%
0%
75.0%
87.5%
100%
Figure 4. LT3965/LT3965-1 Down Transition Dimming Curve
NUMBER OF STEPS
0
DIMMING VALUE (1 TO 255)
96
128
160
60
100
3865 F03
64
32
0
20 40 80
192
224
256
PWM DIMMING (0.4% TO 99.6%)
37.5%
50.0%
62.5%
25.0%
12.5%
0%
75.0%
87.5%
100%
Figure 3. LT3965/LT3965-1 Up Transition Dimming Curve

LT3965IFE-1#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
LED Lighting Drivers Octal Matrix LED Bypass Switch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union