LT3965/LT3965-1
8
39651fa
For more information www.linear.com/LT3965
PIN FUNCTIONS
V
IN
: Input Supply Pin for LED Bypass Switches and Fault
Detectors. Must be locally by-passed with a 1µF (or larger)
capacitor placed close to this pin. For proper channel switch
bypass operation, V
IN
must be at least 7.1V higher than
channel source voltage.
EN/UVLO: Shutdown and Undervoltage Detect Pin. An
accurate 1.24V (nominal) falling threshold with exter
-
nally programmable
hysteresis detects when V
IN
– SRC
is okay to enable the part. Rising hysteresis is generated
by an external resistor and an accurate internal 2.7µA
pull-down current. EN/UVLO going high (from below the
falling threshold to above the rising threshold) resets the
device to an initial power-on condition, which all registers
are loaded with a default value. Tie to 0.4V, or less, to dis
-
able the device and reduce V
DD
and V
IN
quiescent current
below 1µA. Typically this pin is tied to a PNP based level
shifter to ensure the part is enabled only when V
IN
is at
least 7.1V higher than channel source voltage.
ALERT: Alert Output for Fault Condition Report. ALERT pin
is asserted (pulled low) to indicate that an open LED fault
condition or/and a shorted
LED fault condition or/and an
overheat
fault condition are detected. The ALERT pin is
deasserted (released to high) after the part sends its Alert
Response Address successfully or the fault condition is
cleared by an I
2
C write command.
RTCLK: External PWM Clock Input and Internal Oscillator
Frequency Programming Pin. Set the internal oscillator
frequency using a resistor to GND if the internal oscillator
is used for PWM dimming. An external clock source able
to sink 500µA at 0.4V can be used for PWM dimming by
driving RTCLK above and below V
IH
and V
IL
respectively
to override the internal oscillator. Do not leave the RTCLK
pin open. Place the resistor close to the IC if a resistor is
used to set the internal oscillator frequency. LED PWM
dimming frequency equals the programmed internal os
-
cillator frequency
divided by 2048 or the external clock
frequency divided by 2048.
LEDREF: LED Reference Voltage Input. This pin is used to
set the normal operating V
F
of the LED. The shorted LED
threshold V
STH
can be programmed through I
2
C Serial
Interface to one of the following four values: 1V, V
LEDREF
+ 1V, 2 • V
LEDREF
+ 1V and 3 • V
LEDREF
+ 1V. Connecting
this pin to GND sets the shorted LED threshold to 1V.
The
internal value of V
LEDREF
becomes fixed at 4V if more
than 4V is applied to this pin. Do not leave this pin open.
V
DD
: Supply Voltage for I
2
C Serial Port and Input Supply
Pin for Internal Bias and Logic. This pin sets the logic
reference level of I
2
C SCL and SDA pins. SCL and SDA
logic levels are scaled to V
DD
. When the V
DD
pin is 2.7V or
above, the I
2
C interface is active. The LT3965/LT3965-1
will acknowledge communications to its address and data
can be written to and read back from LT3965/LT3965-1
registers. This is true even if EN/UVLO is low. However,
when EN/UVLO goes high, the LT3965/LT3965-1 resets
all registers to default values (see Table 1 and Table 2 for
default values). Connect a 0.1μF (or larger) decoupling
capacitor from this pin to ground.
SCL: Clock Input Pin for the I
2
C Serial Port. The I
2
C logic
levels are scaled with respect to V
DD
.
SDA: Data Input and Output Pin for the I
2
C Serial Port. The
I
2
C logic levels are scaled with respect to V
DD
.
ADDR[4:1]: Programmable Address Select Pins. The device
address is 010xxxx0 for all channel mode (ACMODE) write,
010xxxx1 for all channel mode (ACMODE) read, 101xxxx0
for single channel mode (SCMODE) write, and 101xxxx1
for single channel mode (SCMODE) read. ADDR[4] is
MSB and ADDR[1] is LSB. A total of 16 LT3965/LT3965-1
devices can be connected to the same I
2
C bus. ADDR[4:1]
are pulled up to V
DD
through a 500k resistor inside the
LT3965/LT3965-1, so ADDR[4:1] default value is 1111.
Each bit of ADDR[4:1] default value can be overwritten by
connecting the pin to the ground. For robust design, use an
external resistor to connect ADDR pins to V
DD
or to GND.
DRN[8:1]: Floating N-Channel FET Drain Side Pins. Tie to
V
DD
with a 100k resistor if not used.
SRC[8:1]: Floating N-Channel FET Source Side Pins. The
channel source voltage (SRC[8:1]) must be at least 7.1V
lower than V
IN
for proper channel switch bypass operation.
Tie to GND if not used.
GND: Exposed Pad Pin. Solder the exposed pad directly
to ground plane (GND).
