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9DBV0831AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 10 REVISION H 04/28/16
9DBV0831 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = T
COM
or T
IND
; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in High BW Mode 2 2.7 4 MHz 1,5
-3dB point in Low BW Mode 1 1.4 2 MHz 1,5
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 1.1 2 dB 1
Duty Cycle t
D
C
Measured differentially, PLL Mode 45 50.1 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode @100MHz -1 0.02 1 % 1,3
t
p
dBYP
Bypass Mode, V
T
= 50% 3000 3636 4400 ps 1
t
p
dPLL
PLL Mode V
T
= 50% 0 81 200 ps 1,4
Skew, Output to Output t
sk3
V
T
= 50% 29 50 ps 1,4
PLL mode 13.0 50 ps 1,2
Additive Jitter in Bypass Mode 0.1 25 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
5
The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
PLL Bandwidth BW
TA = T
COM
or T
IND
; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 33 52 86 ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.9 1.4 3
ps
(rms)
1,2,3,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.1 2.5
3.1
ps
(rms)
1,2,3,5
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.5 0.6
1
ps
(rms)
1,2,3,5
t
jphSGMII
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
0.0 2.0 NA
ps
(rms)
1,6
t
jphPCIeG1
PCIe Gen 1 0.1 2.4 N/A
ps
(p-p)
1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.4 N/A
ps
(rms)
1,2,3,4,
5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.1 0.1 N/A
ps
(rms)
1,2,3,4
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
165 200 N/A
ps
(rms)
1,2,3,4
t
jphSGMII
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
251 300 N/A
fs
(rms)
1,6
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
4
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5
Driven by 9FGV0831 or equivalent
6
Driven by Rohde&Schwarz SMA100
Additive Phase Jitter,
Bypass Mode
t
jphPCIeG2
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This fi
g
ures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Phase Jitter, PLL Mode
t
jphPCIeG2
REVISION H 04/28/16 11 8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB)
9DBV0831 DATASHEET
Additive Phase Jitter Plot: 125M (12kHz to 20MHz)
RMSaddi tvejitte r:
8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 12 REVISION H 04/28/16
9DBV0831 DATASHEET
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Note: SMBus address is latched on SADR pin.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9DBV0831AKILF

Mfr. #:
Buy 9DBV0831AKILF
Manufacturer:
IDT
Description:
Clock Buffer 8 O/P VERY LOW POWER PCIE G3
Lifecycle:
New from this manufacturer.
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