8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 18 REVISION H 04/28/16
9DBV0831 DATASHEET
Ordering Information
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Part / Order Number Shipping Packaging Package Temperature
9DBV0831AKLF Trays 48-pin VFQFPN 0 to +70° C
9DBV0831AKLFT Tape and Reel 48-pin VFQFPN 0 to +70° C
9DBV0831AKILF Trays 48-pin VFQFPN -40 to +85° C
9DBV0831AKILFT Tape and Reel 48-pin VFQFPN -40 to +85° C
Rev. Issue Date Initiator Description Page #
A 3/22/21012 RDW
1. Updated electrical tables with typical data from characterization.
2. Updated ordering information to indicate B rev device.
3. Data sheet title change to indicate PCIe Gen1/2/3.
4. Move to preliminary.
Various
B 7/6/2012 RDW
1. Extensive changes to page 1 text: Description, Recommended
Application, Output Features, Features/Benefits, DS Title.
2. Indicated default value in Frequency Select Table.
3. Pins 3,4 changed from FB,FB# to FB_DNC,FB_DNC# to indicate that
these pins are Do Not Connect (DNC).
1-3
C 7/10/2012 RDW 1. Removed 156.25M from input frequency specification.
D 8/13/2012 RDW
1. Removed "Differential" from DS title and Recommended Application,
corrected typo's in Description.
2. Removed references to 60KOhm pulldown under pinout.
3. Updated "Phase Jitter Parameters" table by adding "Industry Limit"
column and updated all Electrical Tables with characterization data.
4. Updated Byte3[0] to be consistent with Byte 2. Updated Byte6[7:6]
definition.
5. Updated Mark spec with correct part revision (A) and added thermal
data to page 13.
6. Added NDG48 to "Package Outline and Package Dimensions" on page
14 and updated Ordering information to correct part revision (A rev).
7. Move to final.
1,2,6-
9,11,13,14
E 2/25/2013 RDW
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to
0.6*VDD.
7
F 8/12/2014 RDW Changed package designator from "MLF" to "VFQFPN" Various
G 3/2/2015 RDW
1. Minor formatting updates to electrical tables
2. Added callout for EPAD
3. Updated block diagram to latest format.
4. Updated front page text to latest format.
5. Added additive phase jitter plot.
6. Corrected Byte 2 and Byte 5 in SMBus.
Various
H 4/28/2016
RDW
1. Updated max frequency of 100MHz PLL mode to 140MHz
2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
8
