DATASHEET
9DBV0831 REVISION H 04/28/16 1 ©2016 Integrated Device Technology, Inc.
8-output 1.8V PCIe Gen1/2/3
Zero-Delay/Fan-out Buffer (ZDB/FOB)
9DBV0831
Description
The 9DBV0831 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 8 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
• 8 – 1-200Hz Low-Power (LP) HCSL DIF pairs
w/Z
O=100ohms
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms for 12k-20MHz
Features/Benefits
• LP-HCSL outputs save 16 resistors; minimal board space
and BOM cost
• 62mW typical power consumption in PLL mode; minimal
power consumption
• Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Block Diagram
CONTROL
LOGIC
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SS-
Compatible
PLL
vOE(7:0)#
SCLK_3.3
vSADR
CLK_IN
C
L
K
_
I
N
#
8
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
DIF6
DIF7
