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9DBV0831AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
REVISION H 04/28/16 7 8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB)
9DBV0831 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0831. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
Supply Voltage VDDx -0.5 2.5 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5 V 1,3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6 V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 200 725 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 50 55 % 1
Input Jitter - Cycle to Cycle J
DIFI n
Differential Measurement 0 150 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 8 REVISION H 04/28/16
9DBV0831 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Volta
g
e VDDx Supply volta
g
e for core and analo
g
1.7 1.8 1.9 V
Output Supply Volta
g
e VDDIO Supply volta
g
e for Low Power HCSL Outputs 0.95 1.05 1.9 V
Commmercial range 0 25 70 °C
Industrial range -40 25 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.6 V
DD
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA
F
ib
yp
Bypass mode 1 200 MHz 2
F
i
p
ll
100MHz PLL mode 60 100.00 140 MHz 2
F
i
p
ll
125MHz PLL mode 75 125.00 175 MHz 2
F
i
p
ll
50MHz PLL mode 30 50.00 65 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,5
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms1,2
Input SS Modulation
Frequency PCIe
f
MODI NPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30 33 kHz
Input SS Modulation
Frequency non-PCIe
f
MODI N
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
066kHz
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.6 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 4
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
Bus Voltage 1.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 6
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
5
DIF_IN input
6
The differential input clock must be runnin
g
for the SMBus to be active
4
For V
DDSMB
< 3.3V, V
IHSMB
>= 0.8xV
DDSMB
Ambient Operating
Temperature
T
AMB
Input Current
Input Frequency
Capacitance
REVISION H 04/28/16 9 8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB)
9DBV0831 DATASHEET
Electrical Characteristics–Low Power HCSL Outputs
Electrical Characteristics–Current Consumption
TA = T
COM
or T
IND
; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
dV/dt Scope avera
g
in
g
on, fast settin
g
1.7 2.7 4
V/ns
1,2,3
dV/dt Scope averaging on, slow setting 1.2 2.1 3.3
V/ns
1,2,3
Slew rate matchin
g
Δ
dV/dt Slew rate matchin
g
, Scope avera
g
in
g
on 4.6 20
%
1,2,4
Voltage High V
HIGH
660 774 850 7
Voltage Low V
LOW
-150 18 150 7
Max Volta
g
e Vmax 820 1150 7
Min Volta
g
eVmin -300-25 7
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1528 mV 1,2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 413 550 mV 1,5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 11 140 mV 1,6
2
Measured from differential waveform
7
At default SMBus settings.
Slew rate
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope avera
g
in
g
off)
mV
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
Δ
-Vcross to be smaller than Vcross absolute.
TA = T
COM
or T
IND
; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDA
VDDA+VDDR, PLL Mode, @100MHz 11 15 mA
I
DD
VDD, All outputs active @100MHz 7 10 mA
I
DDO
VDDO, All outputs active @100MHz 28 35 mA
I
DDAPD
VDDA+VDDR, PLL Mode, @100MHz 0.6 1 mA 2
I
DDPD
VDD, Outputs Low/Low 1 2 mA 2
I
DDOPD
VDDO,Outputs Low/Low 0 0.01 mA 2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input clock stopped.
Operating Supply Current
Powerdown Current
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9DBV0831AKLF

Mfr. #:
Buy 9DBV0831AKLF
Manufacturer:
IDT
Description:
Clock Buffer PCIe BUFFER, 8 OUT GEN 1/2/3, LOW POWER
Lifecycle:
New from this manufacturer.
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