LTC4150
5
4150fc
PIN FUNCTIONS
SENSE
+
(Pin 1): Positive Sense Input. This is the nonin-
verting current sense input. Connect SENSE
+
to the load
and charger side of the sense resistor. Full-scale current
sense input is 50mV. SENSE
+
must be within 60mV of
V
DD
for proper operation.
SENSE
–
(Pin 2): Negative Sense Input. This is the inverting
current sense input. Connect SENSE
–
to the positive bat-
tery terminal side of the sense resistor. Full-scale current
sense input is 50mV. SENSE
–
mus t be within 6 0mV of V
DD
for proper operation.
C
F
+
(Pin 3): Filter Capacitor Positive Input. A capacitor
connected between C
F
+
and C
F
–
fi lters and averages
noise and fast battery current variations. A 4.7μF value
is recommended. If fi ltering is not desired, leave C
F
+
and
C
F
–
unconnected.
C
F
–
(Pin 4): Filter Capacitor Negative Input. A capacitor
connected between C
F
+
and C
F
–
fi lters and averages
noise and fast battery current variations. A 4.7μF value
is recommended. If fi ltering is not desired, leave C
F
+
and
C
F
–
unconnected.
SHDN (Pin 5): S h u t d o w n D i g i t a l I n p u t . W h e n a s s e r t e d l o w ,
SHDN forces the LTC4150 into its low current consumption
power-down mode and resets the part. In applications
with logic supply V
CC
> V
DD
, a resistive divider must be
used between SHDN and the logic which drives it. See the
Applications Information section.
POL (Pin 6): Battery Current Polarity Open-Drain Output.
POL indicates the most recent battery current polarity when
INT is high. A low state indicates the current is fl owing out
of the battery while high impedance means the current
is going into the battery. POL latches its state when INT
is asserted low. POL is an open-drain output and can be
pulled up to any logic supply up to 9V. In shutdown, POL
is high impedance.
GND (Pin 7): Ground. Connect directly to the negative
battery terminal.
V
DD
(Pin 8): Positive Power Supply. Connect to the load
and charger side of the sense resistor. SENSE
+
also con-
nects to V
DD
. V
DD
operating range is 2.7V to 8.5V. Bypass
V
DD
with 4.7μF capacitor.
CLR (Pin 9): Clear Interrupt Digital Input. When asserted
low for more than 20μs, CLR resets INT high. Charge
counting is unaffected. INT may be directly connected to
CLR. In this case the LTC4150 will capture each assertion
of INT and wait at least 1μs before resetting it. This ensures
that IN T pulses low for at least 1μs but gives automatic
INT reset. In applications with a logic supply V
CC
> V
DD
,
a resistive divider must be used between INT and CLR.
See the Applications Information section.
INT (Pin 10): Charge Count Interrupt Open-Drain Output.
INT latches low every 1/(V
SENSE
• G
VF
) seconds and is
reset by a low pulse at CLR. INT is an open-drain output
and can be pulled up to any logic supply of up to 9V. In
shutdown IN T is high impedance.
