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NB3U1548CDG

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. 4
1 Publication Order Number:
NB3U1548C/D
NB3U1548C
3.3V/2.5V/1.8V/1.5V 160 MHz
1:4 LVCMOS/LVTTL Low
Skew Over Voltage Tolerant
Fanout Buffer
Description
The NB3U1548C is an LVCMOS, overvoltage tolerant clock fanout
buffer targeted for clock generation in high performance
telecommunication, networking and computing applications. The
device is optimized for low skew clock distribution in low voltage
applications. The input overvoltage tolerance enables using this
device in mixed mode voltage applications. An output enable pin
controls whether the outputs are in the active or high impedance state.
Guaranteed output skew characteristics make the NB3U1548C ideal
for those applications demanding well defined performance and
repeatability. The NB3U1548C is packaged in a small SOIC−8 and in
an TSSOP−8 package.
Features
• Low skew 1:4 Fanout Buffer
• Supports 3.3 V, 2.5 V, 1.8 V and 1.5 V Power Supplies
• LVCMOS Input and Output Levels
• 3.6 V Overvoltage Tolerance at the Clock and Control Inputs
• Supports Clock Frequencies up to 160 MHz
• LVCMOS Compatible Control Input for Output Disable
• Output Disabled to a High Impedance State
• −40°C to 85°C Ambient Operating Temperature
• Available in Pb−Free RoHS Compliant Packages (SOIC−8,
TSSOP−8)
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. Block Diagram
MARKING
DIAGRAMS
A = Assembly Location
L = Wafer Lot
Y = Year
W, WW = Work Week
G = Pb−Free Package
SOIC−8
D SUFFIX
CASE 751
See detailed ordering and shipping information on page 9 o
f
this data sheet.
ORDERING INFORMATION
1548C
ALYWG
G
1
8
(Note: Microdot may be in either location)
1
8
TSSOP−8
DT SUFFIX
CASE 948S
154
YWW
AG
1
8
1
8
www.onsemi.com
NB3U1548C
www.onsemi.com
2
Figure 2. Pin Configuration (Top View)
OE
V
DD
GND
Q4
CLK_IN
Q1
Q2
Q3
1
2
3
4
8
7
6
5
Table 1. PIN DESCRIPTIONS
Number Name Type Description
1 CLK_IN Input Pulldown Single−ended clock input. LVCMOS interface levels.
2 Q1 Output Single−ended clock output. LVCMOS interface levels.
3 Q2 Output Single−ended clock output. LVCMOS interface levels.
4 Q3 Output Single−ended clock output. LVCMOS interface levels.
5 Q4 Output Single−ended clock output. LVCMOS interface levels.
6 GND Power Power supply ground.
7 VDD Power Power supply pin.
8 OE Input Pullup Output enable pin. See Table 3. LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Min Typ Max Units
CIN Input Capacitance 4 pF
CPD Power Dissipation Capacitance
V
DD
= 3.465 V 14 pF
V
DD
= 2.375 V 13 pF
V
DD
= 1.95 V 13 pF
V
DD
= 1.6 V 12 pF
RPULLUP Input Pullup Resistor 51
kW
RPULLDOWN Input Pulldown Resistor 51
kW
ROUT Output Impedance
V
DD
= 3.3 V ± 5% 9
W
V
DD
= 2.5 V ± 5% 10
W
V
DD
= 1.8 V ± 0.15 V 12
W
V
DD
= 1.5 ± 0.1 V 15
W
Function Table
Table 3. OE CONFIGURATION TABLE
Input
Operation
OE
0 Q[4:1] disabled (high−impedance)
1 (default) Q[4:1] enabled
NOTE: OE is an asynchronous control.
NB3U1548C
www.onsemi.com
3
Table 4. ABSOLUTE MAXIMUM RATINGS
Item Rating
Supply Voltage, V
DD
4.6 V
Inputs, V
I
3.6 V
Outputs, V
O
−0.5 V to V
DD
+ 0.5 V
Package Thermal Impedance, θ
JA
8 Lead SOIC
8 Lead TSSOP
102.5°C/W (0 mps)
151.2°C/W (0 mps)
Storage Temperature, T
STG
−65°C to 150°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 6 cm
2
copper area.
2. For additional information, see Application Note AND8003/D.
Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Min Typ Max Units
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3 V + 5%, T
A
= −405C to 855C
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
I
DDQ
Quiescent Power Supply Current Inputs Open, Outputs
Unloaded
1 mA
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 2.5 V + 5%, T
A
= −405C to 855C
V
DD
Power Supply Voltage 2.375 2.5 2.625 V
I
DDQ
Quiescent Power Supply Current Inputs Open, Outputs
Unloaded
1 mA
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 1.8 V + 0.15 V, T
A
= −405C to 855C
V
DD
Power Supply Voltage 1.65 1.8 1.95 V
I
DDQ
Quiescent Power Supply Current Inputs Open, Outputs
Unloaded
1 mA
POWER SUPPLY DC CHARACTERISTICS, V
DD
= 1.5 V + 0.1 V, T
A
= −405C to 855C
V
DD
Power Supply Voltage 1.4 1.5 1.6 V
I
DDQ
Quiescent Power Supply Current Inputs Open, Outputs
Unloaded
1 mA
LVCMOS DC CHARACTERISTICS, V
DD
= 3.3 V + 5%, T
A
= −405C to 855C
V
IH
Input High Voltage 0.65 * V
DD
3.6 V
V
IL
Input Low Voltage −0.3 0.35 * V
DD
V
I
IH
Input High Current
CLK_IN V
DD
= V
IN
= 3.465 V 165
mA
OE V
DD
= V
IN
= 3.465 V 5
mA
I
IL
Input Low Current
CLK_IN V
DD
= 3.465 V, V
IN
= 0 V −5
mA
OE V
DD
= 3.465 V, V
IN
= 0 V −150
mA
V
OH
Output High Voltage Q[4:1] I
OH
= −12 mA 2.6 V
V
OL
Output Low Voltage Q[4:1] I
OL
= 12 mA 0.5 V
LVCMOS DC CHARACTERISTICS, V
DD
= 2.5 V + 5%, T
A
= −405C to 855C
V
IH
Input High Voltage 0.65 * V
DD
3.6 V
V
IL
Input Low Voltage −0.3 0.35 * V
DD
V
I
IH
Input High Current
CLK_IN V
DD
= V
IN
= 2.625 V 165
mA
OE V
DD
= V
IN
= 2.625 V 5
mA
I
IL
Input Low Current
CLK_IN V
DD
= 2.625 V, V
IN
= 0 V −5
mA
OE V
DD
= 2.625 V, V
IN
= 0 V −150
mA
P1-P3P4-P6P7-P9P10-P11

NB3U1548CDG

Mfr. #:
Buy NB3U1548CDG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V/2.5V/1.8V/1.5V 160 M
Lifecycle:
New from this manufacturer.
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