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Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol UnitsMaxTypMinTest ConditionsParameter
LVCMOS DC CHARACTERISTICS, V
DD
= 2.5 V + 5%, T
A
= −405C to 855C
V
OH
Output High Voltage Q[4:1] I
OH
= −12 mA 1.8 V
V
OL
Output Low Voltage Q[4:1] I
OL
= 12 mA 0.5 V
LVCMOS DC CHARACTERISTICS, V
DD
= 1.8 V + 0.15 V, T
A
= −405C to 855C
V
IH
Input High Voltage 0.65 * V
DD
3.6 V
V
IL
Input Low Voltage −0.3 0.35 * V
DD
V
I
IH
Input High Current
CLK_IN V
DD
= V
IN
= 1.95 V 165
mA
OE 5
mA
I
IL
Input Low Current
CLK_IN V
DD
= 1.95 V, V
IN
= 0 V −5
mA
OE V
DD
= 1.95 V, V
IN
= 0 V −150
mA
V
OH
Output High Voltage Q[4:1] I
OH
= −6 mA V
DD
– 0.45 V
V
OL
Output Low Voltage Q[4:1] I
OL
= 6 mA 0.45 V
LVCMOS DC CHARACTERISTICS, V
DD
= 1.5 V + 0.1 V, T
A
= −405C to 855C
V
IH
Input High Voltage 0.65 * V
DD
3.6 V
V
IL
Input Low Voltage −0.3 0.35 * V
DD
V
I
IH
Input High Current
CLK_IN V
DD
= V
IN
= 1.6 V 165
mA
OE V
DD
= V
IN
= 1.6 V 5
mA
I
IL
Input Low Current
CLK_IN V
DD
= 1.6 V, V
IN
= 0 V −5
mA
OE V
DD
= 1.6 V, V
IN
= 0 V −150
mA
V
OH
Output High Voltage Q[4:1] I
OH
= −4 mA 0.75 * V
DD
V
V
OL
Output Low Voltage Q[4:1] I
OL
= 4 mA 0.25 * V
DD
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Min Typ Max Units
AC CHARACTERISTICS, V
DD
= 3.3 V + 5%, T
A
= −405C to 855C
f
OUT
Output Frequency 160 MHz
tp
LH
Propagation Delay
(low to high transition); (Notes 4, 8)
0.7 2.1 ns
tp
HL
Propagation Delay
(high to low transition); (Notes 4, 8)
0.7 2.1 ns
t
PLZ
, t
PHZ
Disable Time, (active to high−impedance) 10 ns
t
PZL
, t
PZH
Enable Time, (high−impedance to active) 10 ns
tsk(o) Output Skew; (Notes 5, 6) 250 ps
tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps
tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range:
12 kHz − 5 MHz
0.094 ps
t
R
/ t
F
Output Rise/Fall Time 10% to 90% 0.33 1.2 ns
odc Output Duty Cycle 48 53 %
AC CHARACTERISTICS, V
DD
= 2.5 V + 5%, T
A
= −405C to 855C
f
OUT
Output Frequency 160 MHz
tp
LH
Propagation Delay
(low to high transition); (Notes 4, 8)
0.8 2.0 ns
tp
HL
Propagation Delay
(high to low transition); (Notes 4, 8)
0.8 2.0 ns
t
PLZ
, t
PHZ
Disable Time (active to high−impedance) 10 ns
t
PZL
, t
PZH
Enable Time (high−impedance to active) 10 ns
tsk(o) Output Skew; (Notes 5, 6) 250 ps
tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps
tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range:
12 kHz − 5 MHz
0.076 ps
t
R
/ t
F
Output Rise/Fall Time 10% to 90% 0.33 1.2 ns
odc Output Duty Cycle 45 53 %
AC CHARACTERISTICS, V
DD
= 1.8 V + 0.15 V, T
A
= −405C to 855C
f
OUT
Output Frequency 160 MHz
tp
LH
Propagation Delay
(low to high transition); (Notes 4, 8)
1.1 2.8 ns
tp
HL
Propagation Delay
(high to low transition); (Notes 4, 8)
1.1 2.8 ns
t
PLZ
, t
PHZ
Disable Time (active to high−impedance) 10 ns
t
PZL
, t
PZH
Enable Time (high−impedance to active) 10 ns
tsk(o) Output Skew; (Notes 5, 6) 250 ps
tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps
tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range:
12 kHz − 5MHz
0.193 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Characterized up to F
OUT
150 MHz.
4. Measured from the V
DD
/2 of the input to V
DD
/2 of the output.
5. This parameter is defined in accordance with JEDEC Standard 65.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
8. With rail to rail input clock.
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Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol UnitsMaxTypMinTest ConditionsParameter
AC CHARACTERISTICS, V
DD
= 1.8 V + 0.15 V, T
A
= −405C to 855C
t
R
/ t
F
Output Rise/Fall Time 0.63 V to 1.17 V 0.11 0.6 ns
odc Output Duty Cycle 47 53 %
AC CHARACTERISTICS, V
DD
= 1.5 V + 0.1 V, T
A
= −405C to 855C
f
OUT
Output Frequency 160 MHz
tp
LH
Propagation Delay
(low to high transition); (Notes 4, 8)
1.5 3.5 ns
tp
HL
Propagation Delay
(high to low transition); (Notes 4, 8)
1.5 3.5 ns
t
PLZ
, t
PHZ
Disable Time (active to high−impedance) 10 ns
t
PZL
, t
PZH
Enable Time (high−impedance to active) 10 ns
tsk(o) Output Skew; (Notes 5, 6) 250 ps
tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps
tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range:
12 kHz − 5 MHz
0.266 ps
t
R
/ t
F
Output Rise/Fall Time 0.525 V to 0.975 V 0.11 0.6 ns
odc Output Duty Cycle 47 53 %
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Characterized up to F
OUT
150 MHz.
4. Measured from the V
DD
/2 of the input to V
DD
/2 of the output.
5. This parameter is defined in accordance with JEDEC Standard 65.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
8. With rail to rail input clock.

NB3U1548CDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V/2.5V/1.8V/1.5V 160 M
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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