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ICS9250BF-28

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
13
ICS9250-28
Group Skews (CPU 133 MHz, SDRAM 133MHz)
T
A
= 0 - 70º C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
R
efer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CPU to SDRAM Skew
1
T
sk3 CPU-SDRAM
3.25 3.45 4.25 ns
Skew Window
1
T
w
3 CPU-SDRAM
0 155 500 ps
CPU to 3V66 Skew
1
T
sk3 CPU-3V66
-500 120 500 ps
Skew Window
1
T
w
3 CPU-3V66
0 120 500 ps
SDRAM to 3V66 Skew
1
T
sk3 SDRAM-3V66
-3.25 -3.08 -4.25 ps
Skew Window
1
T
w
3 SDRAM-3V66
0 175 500 ps
3V66 to PCI Skew
1
T
sk3 3V66-PCI
1.5 2.2 3.5 ns
Skew Window
1
T
w
3 3V66-PCI
0 80 500 ps
I
OAPIC to PCI Skew
1
T
sk3 IOAPIC-PCI
-1 -0.1 1 ns
Skew Window
1
T
w3 IOAPIC-PCI
001ns
1
Guaranteed by design, not 100% tested in production.
Group Skews (CPU133 MHz, SDRAM 100MHz)
T
A
= 0 - 70º C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
R
efer to Group Offset Waveforms diagram for definition of transition edges.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CPU to SDRAM Skew
1
T
sk3 CPU-SDRAM
CPU @ 1.25 V, SDRAM @ 1.5 V -500 -15 500 ps
Skew Window
1
T
w
3 CPU-SDRAM
0 165 500 ps
CPU to 3V66 Skew
1
T
sk3 CPU-3V66
CPU @ 1.25 V, 3V66 @ 1.5 V -500 165 500 ps
Skew Window
1
T
w
3 CPU-3V66
0 105 500 ps
SDRAM to 3V66 Skew
1
T
sk3 SDRAM-3V66
SDRAM, 3V66 @ 1.5 V -500 185 500 ps
Skew Window
1
T
w
3 SDRAM-3V66
0 185 500 ps
3V66 to PCI Skew
1
T
sk3 3V66-PCI
3V66, PCI @ 1.5 V 1.5 2.2 3.5 ns
Skew Window
1
T
w
3 3V66-PCI
0 60 500 ps
I
OAPIC to PCI Skew
1
T
sk3 IOAPIC-PCI
IOAPIC @ 1.25 V, PCI @ 1.5 V -1 -0.1 1 ns
Skew Window
1
T
w3 IOAPIC-PCI
001ns
1
Guaranteed by design, not 100% tested in production.
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
3V66, PCI @ 1.5 V
IOAPIC @ 1.25 V, PCI @ 1.5 V
CPU @ 1.25 V, SDRAM @ 1.5 V
14
ICS9250-28
Group Offset Waveforms
Cycle Repeats
0ns
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 133MHz
SDRAM 100MHz
3V66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
10ns 20ns 30ns 40ns
15
ICS9250-28
1. The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ICS9250BF-28

Mfr. #:
Buy ICS9250BF-28
Manufacturer:
Description:
IC FREQ GENERATOR/BUFFER 56-SSOP
Lifecycle:
New from this manufacturer.
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