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ICS9250BF-28

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4
ICS9250-28
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
2SF0SF1SFUPCMARDS66V3ICPzHM84FERCIPAOI
00X etatsirTetatsirTetatsirTetatsirTetatsirTetatsirTetatsirT
01X 2/KLCT2/KLCT3/KLCT6/KLCT2/KLCTKLCT6/KLCT
100 zHM6.66zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
110 zHM001zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
10 1 zHM331zHM331zHM6.66zHM3.33zHM84zHM813.41zHM3.33
111 zHM331zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
Truth Table
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3: Undefined bits can be written either as "1 or 0"
tiBnoitpitcseDDWP
7tiB)2etoN(tibdevreseRSCI 0
6tiB)2etoN(tibdevreseRSCI 0
5tiB)2etoN(tibdevreseRSCI 0
4tiB)2etoN(tibdevreseRSCI 0
3tiB)2etoN(tibdevreseRSCI 0
2tiB)3etoN(tibdenifednU X
1tiB)3etoN(tibdenifednU X
0tiB
0tiB0SF1SF
KLCUPC
zHM
MARDS
zHM
66V3
zHM
KLCICP
zHM
CIPAOI
zHM
0
1etoN
000 66.660.00166.6633.3333.33
010 0.0010.00166.6633.3333.33
001 23.33123.33166.6633.3333.33
011 23.3310.00166.6633.3333.33
100 66.660.00166.6633.3333.33
110 0.0010.00166.6633.3333.33
10 1 23.33123.33166.6633.3333.33
111 23.33123.33166.6633.3333.33
5
ICS9250-28
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB- DIdevreseR0)evitcanI/evitcA(
6tiB- DIdevreseR0)evitcanI/evitcA(
5tiB- DIdevreseR0)evitcanI/evitcA(
4tiB- DIdevreseR1)evitcanI/evitcA(
3tiB-
murtcepSdaerpS
)ffO=0/nO=1(
1)evitcanI/evitcA(
2tiB721zHM841)evitcanI/evitcA(
1tiB620zHM841)evitcanI/evitcA(
0tiB- DIdevreseR0)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB837MARDS1)evitcanI/evitcA(
6tiB146MARDS1)evitcanI/evitcA(
5tiB245MARDS1)evitcanI/evitcA(
4tiB544MARDS1)evitcanI/evitcA(
3tiB643MARDS1)evitcanI/evitcA(
2tiB742MARDS1)evitcanI/evitcA(
1tiB051MARDS1)evitcanI/evitcA(
0tiB150MARDS1)evitcanI/evitcA(
Note: Reserved ID bits must be written as "0"
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
tiB#niPemaNDWPnoitpircseD
7tiB21)PGA(2-66V31)evitcanI/evitcA(
6tiB9221MARDS1)evitcanI/evitcA(
5tiB2311MARDS1)evitcanI/evitcA(
4tiB3301MARDS1)evitcanI/evitcA(
3tiB639MARDS1)evitcanI/evitcA(
2tiB738MARDS1)evitcanI/evitcA(
1tiB611KLCICP1)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
6
ICS9250-28
Group Timing Relationship Table
1
Byte 4: Reserved Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB- devreseR0)evitcanI/evitcA(
5tiB- devreseR0)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
puorGzHM66UPC
zHM001MARDS
zHM001UPC
zHM001MARDS
zHM331UPC
zHM001MARDS
zHM331UPC
zHM331MARDS
tesffOecnareloTtesffOecnareloTtesffOecnareloTtesffOecnareloT
MARDSotUPCsn5.2-sp005sn0.5sp005sn0.0sp005sn57.3sp005
66V3otUPCsn5.7sp005sn0.5sp005sn0.0sp005sn0.0sp005
66V3otMARDSsn0.0sp005sn0.0sp005sn0.0sp005sn57.3-sp005
ICPot66V3sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005
ICPotICPsn0.0sp005sn0.0sp005sp005sn0.1sn0.0sp005
TOD&BSUhcnysAA/NhcnysAA/NhcnysAA/NhcnysAA/N
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ICS9250BF-28

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Buy ICS9250BF-28
Manufacturer:
Description:
IC FREQ GENERATOR/BUFFER 56-SSOP
Lifecycle:
New from this manufacturer.
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