7
ICS9250-28
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Maximum Case Operating Temperature . . . . . . +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
H
2V
DD
+0.3 V
Input Low Voltage V
L
V
SS
-0.3 0.8 V
Input High Current I
H
V
N
= V
DD
-5 5
µA
I
L1
V
N
= 0 V; Inputs with no pull-up resistors -5
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
C
= 0 pF; @ 66/100 MHz 138 200
C
= 0 pF; @ 100/100 MHz 126 200
C
= 0 pF; @ 133/133 MHz 172 200
C
= 0 pF; @ 133/100 MHz 141 200
C
= Max loads; @ 66/100 MHz 339 400
C
= Max loads; @ 100/100 MHz 328 400
C
= Max loads; @ 133/133 MHz 383 450
C
= Max loads; @ 133/100 MHz 340 400
C
= 0 pF; @ 66/100 MHz 9 15
C
= 0 pF; @ 100/100 MHz 11 18
C
= 0 pF; @ 133/133 MHz 13 20
C
= 0 pF; @ 133/100 MHz 13 20
C
= Max loads; @ 66/100 MHz 13 35
C
= Max loads; @ 100/100 MHz 23 60
C
= Max loads; @ 133/133 MHz 29 60
C
= Max loads; @ 133/100 MHz 30 60
I
DD3.3PD
C
= Max loads
251 400
I
DD.25PD
Input address VDD or GND
<1 10
Input Frequency F
i
V
DD
= 3.3 V 12 14.318 16 MHz
Transition time
1
T
trans
To 1st crossing of target frequency 3 ms
Settling time
1
T
s
From 1st crossing to 1% target frequency 3 ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency 3 ms
t
PZH
,t
PZL
Output enable delay (all outputs) 1 10 ns
t
PHZ
,t
PLZ
Output disable delay (all outputs) 1 10 ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
mA
mA
I
DD2.5OP
µA
Powerdown Current
Operating Supply
Current
Input Low Current
µA
mA
mA
I
DD3.3OP