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PCF8598C-2P/02,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I
2
C-bus interface
Product data Rev. 06 — 22 October 2004 7 of 21
9397 750 14219
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
end of data to the slave transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
8.1.3 Device addressing
Following a START condition, the bus master must output the address of the slave it
is accessing. The address of the PCF8598C-2 is shown in Figure 4. To conserve
power, no internal pull-up resistors are incorporated on the hardware selectable pins
and they must be connected to either V
DD
or V
SS
.
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read operation is selected, while a logic 0 selects a write operation.
8.1.4 Write operations
A write-protection input at Pin 1 (WP) allows disabling of write commands from the
master by a hardware signal. Write accesses are allowed to either the upper or lower
512 bytes of the EEPROM if the pin WP is LOW or the lower 512 bytes of the
EEPROM if the pin WP is HIGH. When the pin WP is HIGH the upper 512 bytes of
the EEPROM are write-protected and no acknowledge will be given by the
PCF8598C-2 when data is sent. However, an acknowledge will be given after the
slave address and the word address.
Byte/word write: For a write operation, the PCF8598C-2 requires a second address
field. This address field is a word address providing access to the 256 words of
memory. Upon receipt of the word address, the PCF8598C-2 responds with an
acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition or transmit up to six more
bytes of data and then terminate by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is 10 ms per byte.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I
2
C-bus.
Fig 4. Slave address.
002aaa257
1010A2A1A0R/W
FIXED
HARDWARE
SELECTABLE
SOFTWARE
SELECTABLE
Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I
2
C-bus interface
Product data Rev. 06 — 22 October 2004 8 of 21
9397 750 14219
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Page write: The PCF8598C-2 is capable of an eight-byte page write operation. It is
initiated in the same manner as the byte write operation. The master can transit eight
data bytes within one transmission. After receipt of each byte, the PCF8598C-2 will
respond with an acknowledge. The typical E/W time in this mode is
9 × 3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms
and sequential writing of these 8 bytes another typical 28 ms.
After the receipt of each data byte, the three low-order bits of the word address are
internally incremented. The high-order five bits of the address remain unchanged.
The slave acknowledges the reception of each data byte with an ACK. The I
2
C-bus
data transfer is terminated by the master after the 8th byte with a STOP condition. If
the master transmits more than eight bytes prior to generating the STOP condition,
no acknowledge will be given on the ninth (and following) data bytes and the whole
transmission will be ignored and no programming will be done. As in the byte write
operation, all inputs are disabled until completion of the internal write cycles.
Fig 5. Auto-increment memory word address; two byte write.
S
0A
SLAVE ADDRESS WORD ADDRESS
AADATA P
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
ADATA
R/W
auto increment
word address
auto increment
word address
MBA701
Fig 6. Page write operation; eight bytes.
S0ASLAVE ADDRESS WORD ADDRESS A A
DATA N
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
R/W
auto increment
word address
acknowledge
from slave
A
DATA N + 1
auto increment
word address
002aaa245
A
acknowledge
from slave
ADATA N + 7
auto increment
word address
last byte
Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I
2
C-bus interface
Product data Rev. 06 — 22 October 2004 9 of 21
9397 750 14219
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.1.5 Read operations
Read operations are initiated in the same manner as write operations with the
exception that the LSB of the slave address is set to logic 1.
There are three basic read operations: current address read, random read, and
sequential read.
Remark: The lower 8 bits of the word address are incremented after each
transmission of a data byte (read or write). The MSB of the word address, which is
defined in the slave address, is not changed when the word address count overflows.
Thus, the word address overflows from 255 to 0, and from 511 to 256.
Fig 7. Master reads PCF8598C-2 slave after setting word address (write word address; read data);
sequential read.
S0ASLAVE ADDRESS WORD ADDRESS A A
SLAVE ADDRESS
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
R/W
acknowledge
from master
A
DATA
auto increment
word address
MBA703
P
no acknowledge
from master
1DATA
auto increment
word address
last byte
R/W
S1
n bytes
at this moment master
transmitter becomes
master receiver and
EEPROM slave receiver
becomes slave transmitter
Fig 8. Master reads PCF8598C-2 immediately after first byte (read mode); current address read.
S
1A
SLAVE ADDRESS DATA
A1DATA
acknowledge
from slave
acknowledge
from master
no acknowledge
from master
R/W
auto increment
word address
MBA704 - 1
auto increment
word address
n bytes last bytes
P
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PCF8598C-2P/02,112

Mfr. #:
Buy PCF8598C-2P/02,112
Manufacturer:
NXP Semiconductors
Description:
IC EEPROM 8K I2C 100KHZ 8DIP
Lifecycle:
New from this manufacturer.
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