7
FN6818.0
December 5, 2008
Pin Descriptions
PIN NUMBER NAME FUNCTION
1, 14, 18, 20 AVDD2 1.8V Analog Supply
2, 7, 10, 19, 21, 24 AVSS Analog Supply Return
3 VREF Reference Voltage Out/In
4 VREFSEL Reference Voltage Select (0:Int 1:Ext)
5 VCM Common-Mode Voltage Output
6, 15, 16, 25 AVDD3 3.3V Analog Supply
8, 9 INP, INN Analog Input Positive, Negative
11-13, 29-32, 62, 63, 67 DNC Do Not Connect
17 CLKDIV Clock Divide by Two (Active Low)
22, 23 CLKN, CLKP Clock Input Complement, True
26, 45, 61 OVSS Output Supply Return
27, 41, 44, 60 OVDD2 1.8V LVDS Supply
28 RST Power On Reset (Active Low)
33, 34 D0N, D0P LVDS Bit 0 (LSB) Output Complement, True
35, 36 D1N, D1P LVDS Bit 1 Output Complement, True
37, 38 D2N, D2P LVDS Bit 2 Output Complement, True
39, 40 D3N, D3P LVDS Bit 3 Output Complement, True
42, 43 CLKOUTN, CLKOUTP LVDS Clock Output Complement, True
46, 47 D4N, D4P LVDS Bit 4 Output Complement, True
48, 49 D5N, D5P LVDS Bit 5 Output Complement, True
50, 51 D6N, D6P LVDS Bit 6 Output Complement, True
52, 53 D7N, D7P LVDS Bit 7 Output Complement, True
54, 55 D8N, D8P LVDS Bit 8 Output Complement, True
56, 57 D9N, D9P LVDS Bit 9 (MSB) Output Complement, True
58, 59 ORN, ORP Over-Range Complement, True
64-66 Connect to OVDD2
68 2SC Two’s Complement Select (Active Low)
Exposed Paddle AVSS Analog Supply Return
KAD2710L
8
FN6818.0
December 5, 2008
Pinout
KAD2710C
(68 LD QFN)
TOP VIEW
2SC
DNC
OVDD2
OVDD2
OVDD2
DNC
DNC
OVSS
OVDD2
ORP
ORN
D9P
D9N
D8P
D8N
D7P
D7N
AVDD2
AVSS
AVDD2
AVSS
CLKN
CLKP
AVSS
AVDD3
OVSS
OVDD2
RST
DNC
DNC
DNC
DNC
D0N
D0P
AVDD2
AVSS
VREF
VREFSEL
VCM
AVDD3
AVSS
INP
INN
AVSS
DNC
DNC
DNC
AVDD2
AVDD3
AVDD3
CLKDIV
KAD2710L
Top View
Not to Scale
D4P
D4N
OVSS
OVDD2
CLKOUTP
CLKOUTN
OVDD2
D3P
D3N
D2P
D2N
D1P
D1N
D6P
D6N
D5P
D5N
68 QFN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
47
46
45
44
43
42
41
40
39
38
37
36
35
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
FIGURE 2. PIN CONFIGURATION
KAD2710L
9
FN6818.0
December 5, 2008
Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, T
A
= +25°C, f
SAMPLE
= 275MSPS, f
IN
= 137MHz,
A
IN
= -0.5dBFS unless noted.
FIGURE 3. SNR AND SFDR vs f
IN
FIGURE 4. HD2 AND HD3 vs f
IN
FIGURE 5. SNR AND SFDR vs A
IN
FIGURE 6. HD2 AND HD3 vs A
IN
FIGURE 7. SNR AND SFDR vs f
SAMPLE
FIGURE 8. HD2 AND HD3 vs f
SAMPLE
50
55
60
65
70
75
80
0 50 100 150 200 250 300 350 400 450 500 550
f
IN
(MHz)
SNR(dBFS), SFDR(dBc)
SNR
SFDR
40
45
50
55
60
65
70
75
-30 -25 -20 -15 -10 -5 0
A
IN
(dBFS)
SNR(dBFS), SFDR(dBc)
SNR
SFDR
50
55
60
65
70
75
80
50 100 150 200 250 300
f
SA MP L E
(f
S
) (MSPS)
SNR(dBFS), SFDR(dBc)
SNR
SFDR
HD2, HD3(dBc
)
KAD2710L

KAD2710L-27Q68

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog to Digital Converters - ADC 10-BIT 275MSPS SINGL ADC PROG
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union