LTC4415
10
4415fa
when the load current decreases below the current limit.
Power consumption in LTC4415 increases during opera-
tion in current limit due to the large voltage drop across
the PFET devices (P1 or P2).
Load Current Monitor
The current limit pins output 1/1000th of the ideal diode
output current. The voltage across the current limit resis-
tor can be measured to monitor the current through each
ideal diode as follows:
I
OUT
=1000
V
CLIM
R
CLIM
Note that the current monitor function via V
CLIM
is not
available when CLIM pins are grounded to use the fixed
internal current limit.
Soft-Start
An internal soft-start is included for each ideal diode to
minimize the start-up inrush current. When either of the
diodes start forward conduction, the load current ramps
from zero to the set current limit over a period of 2ms. The
soft-start can be monitored by observing the CLIM1 and
CLIM2 pin voltages when they are connected to grounded
resistors. Soft-start duration is reduced to 0.5ms (typical)
when the CLIM pins are grounded. In order to minimize
output droop during switchover between input sources
in power supply ORing applications, soft-start is disabled
when the output voltage is above 1.2V.
Forward Conduction Status Monitor
Active low open-drain output status signals, STAT1 and
STAT2, indicate the forward conduction status of each
ideal diode. With resistor pull-ups on these status pins,
a low voltage indicates forward conduction from input to
output, IN1/IN2 to OUT1/OUT2, respectively. The status
pins go to high impedance when the respective ideal diodes
are disabled, during reverse turn-off conditions, or during
thermal shutdown.
Thermal Warning and Shutdown
Thermal sensors within the LTC4415 monitor the die tem-
perature when either of the diodes are enabled. When the
die temperature exceeds the warning threshold (130°C),
the WARN1/WARN2 pins are pulled down with open-drain
NFETs while the LTC4415 continues to operate normally.
This gives some time for the user to reduce the load current
to avoid thermal shutdown. The warning signal is deas-
serted when the die temperature cools down below 115°C.
Thermal shutdown is triggered when the internal die
temperature increases beyond the fault threshold (160°C).
Status pins, STAT1/STAT2, are deasserted during thermal
shutdown to indicate the interruption in forward condi-
tion. Normal operation resumes when the die temperature
cools below 140°C. Note that prolonged operation at the
overtemperature condition degrades device reliability.
Figure 2 shows WARN followed by thermal shutdown
caused by an output short-circuit to ground. Time to
thermal shutdown varies depending on power dissipation,
ambient temperature and board layout. The output cur-
rent ramps up after the device cools down below 140°C,
but shuts down repeatedly as the device overheats due
to persistent short.
operaTion
Figure 2. Current Limit Warning and
Thermal Shutdown on Output Short Circuit
V
OUT
2V/DIV
I
OUT
2A/DIV
10ms/DIV
4415 F02
V
IN
= 3.6V
R
CLIM
= 124Ω
C
OUT
= 4.7µF
STAT
5V/DIV
WARN
5V/DIV
OUTPUT SHORTED
TO GND
RESTART DUE TO
THERMAL HYSTERESIS
THERMAL
SHUTDOWN
The thermal sensors are independent for each diode to
warn of, or shut down the heat generating path so that it
does not hinder the normal operation of the other path.
Depending on the amount of heat generated, the whole
die may still heat up and eventually shut down the other
channel.
LTC4415
11
4415fa
applicaTions inForMaTion
operaTion
Stability Considerations
Any capacitance on the CLIM pins adds a pole to the cur-
rent control loop. Therefore, stray capacitance on these
pins must be kept to a minimum. Although the maximum
allowed value of the current limit adjust resistor is 1000Ω,
any additional capacitance on these pins reduces the
maximum allowed resistance, consequently increasing
the minimum allowed current limit. For stable operation,
the pole frequency at the CLIM pins should be kept above
800kHz. Therefore, if the CLIM pin parasitic capacitance
is C
P
, the following equation should be used to calculate
the maximum allowed resistor R
CLIM
:
R
CLIM
1
2π 800kHz C
P
When the voltage at the CLIM pins are monitored using a
long cable, such as an oscilloscope probe, decouple the
parasitic capacitance of the probe and the monitor system
using a series resistor as shown in Figure 3, where a 20k
resistor has been added between the CLIM pin and the
probe to ensure stable operation.
Input and Output Capacitors
High current transients through parasitic inductance on the
input and output sides of the ideal diodes can cause volt-
age spikes on the IN1/IN2/OUT1/OUT2 pins. These current
transients can occur on power plug-in, load disconnect
or switching, disable, or even thermal shutdown. Limit
inductance and/or increase bypass capacitors to prevent
pin voltages from exceeding the absolute maximum rat-
ing of 6V. Some ESR in these capacitors may be helpful
in dampening the resonances and minimizing the ringing
caused by hot plugging or load switching. Refer to Ap-
plication Note 88, entitled, “Ceramic Input Capacitors Can
Cause Overvoltage Transients” for a detailed discussion
and mitigation of this phenomenon.
The values of the input and output decoupling capacitors
also depends on the maximum allowable droop during
switchover in power supply ORing applications. Typical du-
ration for LTC4415 ideal diodes to switchover from reverse
turn-off to forward conduction, t
SWITCH
, is 9µs. Therefore,
the minimum decoupling capacitance, C, required for a
specified maximum output voltage droop, V, when one
of the input voltages drops, can be calculated as follows:
C =
I
LOAD
t
SWITCH
V
where I
LOAD
is the load current at the time of switchover.
For example, the required value of output capacitance for
a 100mV maximum droop in the output voltage during
quick switchover at 1A load would be 100µF. Note that both
supplies share the load during switchover, and therefore
reduce the droop, when the voltage on the falling supply
pin changes slowly.
Figure 3. Current Monitor with High Capacitance Probe/Instrument
Undervoltage Lockout
Each ideal diode contains an independent UVLO control
circuit so that one input experiencing undervoltage lockout
does not hinder normal operation of the other channel.
The diode conduction path is turned off and the status
signal, STAT1/STAT2, is deasserted during an undervolt-
age condition.
CLIM
PIN
C
P
4415 F03
C
MONITOR
R
CLIM
20k
MONITOR
LTC4415
12
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applicaTions inForMaTion
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be followed to ensure proper operation
of the LTC4415:
1. Connect the exposed pad of the package (Pin 17) directly
to a large PC board ground to minimize thermal imped-
ance. Correctly soldered to a 2500mm
2
double-sided 1oz
copper board, the DFN package has a thermal resistance
(θ
JA
) of approximately 43°C/W. Failure to make good
contact between the exposed pad on the backside of
the package and an adequately sized ground plane re-
sults in much larger thermal resistance, raising the die
temperature for given power dissipation. An example
layout for double layer board is given in Figure 4. Via
holes are used in the board under and near the device
to conduct heat away from the device to the bottom
layer.
2. The traces to the input supplies, outputs and their
decoupling capacitors should be short and wide to
minimize the impact of parasitic inductance. Connect
the GND side of the capacitors directly to the ground
plane of the board. The decoupling capacitors provide
the transient current to the internal power MOSFETs
and their drivers.
3. Minimize the parasitic capacitance on CLIM1 and CLIM2
pins for stable operation.
Figure 4. Example Board Layout for a Double-Sided PCB
EN1
IN1
IN2
OUT1
OUT2
4415 F04
CLIM1
CLIM2
WARN1
WARN2
STAT1
STAT2EN2

LTC4415IDHC#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC 2x 4A Ideal Diodes w/ Adj C Lim
Lifecycle:
New from this manufacturer.
Delivery:
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