RT7277
10
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To prevent enabling circuit when V
IN
is smaller than the
V
OUT
target value, a resistive voltage divider can be placed
between the input voltage and ground and connected to
the EN pin to adjust IC lockout threshold, as shown in
Figure 3. For example, if an 8V output voltage is regulated
from a 12V input voltage, the resistor R
EN2
can be selected
to set input lockout threshold larger than 8V.
Application Information
The RT7277 is a synchronous high voltage Buck converter
that can support the input voltage range from 4.5V to 18V
and the output current up to 3A. It adopts ACOT
TM
mode
control to provide a very fast transient response with few
external compensation components.
PWM Operation
It is suitable for low external component count
configuration with appropriate amount of Equivalent Series
Resistance (ESR) capacitors at the output. The output
ripple valley voltage is monitored at a feedback point
voltage. The synchronous high side MOSFET is turned
on at the beginning of each cycle. After the internal on-
time timer expires, the MOSFET is turned off. The pulse
width of this on-time is determined by the converter's input
and output voltages to keep the frequency fairly constant
over the entire input voltage range.
Advanced Constant On-Time Control
The RT7277 has a unique circuit which sets the on-time
by monitoring the input voltage and SW signal. The circuit
ensures the switching frequency operating at 700kHz over
input voltage range and loading range.
Soft-Start
The RT7277 contains an external soft-start clamp that
gradually raises the output voltage. The soft-start timing
can be programmed by the external capacitor between
SS pin and GND. The chip provides a 2μA charge current
for the external capacitor. If a 3.9nF capacitor is used,
the soft-start will be 2.6ms (typ.). The available capacitance
range is from 2.7nF to 220nF.
SS
SS
C5 (nF) 1.365
t (ms) =
I (A)
×
μ
Chip Enable Operation
The EN pin is the chip enable input. Pulling the EN pin
low (<0.4V) will shut down the device. During shutdown
mode, the RT7277 quiescent current drops to lower than
10μA. Driving the EN pin high (>2V, <18V) will turn on the
Figure 1. External Timing Control
An external MOSFET can be added to implement digital
control on the EN pin when no system voltage above 2V
is available, as shown in Figure 2. In this case, a 100kΩ
pull-up resistor, R
EN
, is connected between V
IN
and the
EN pin. MOSFET Q1 will be under logic control to pull
down the EN pin.
RT7277
EN
GND
V
IN
R
EN
C
EN
EN
Figure 2. Digital Enable Control Circuit
Figure 3. Resistor Divider for Lockout Threshold Setting
RT7277
EN
GND
V
IN
R
EN1
R
EN2
RT7277
EN
GND
100k
V
IN
R
EN
Q1
EN
device again. For external timing control, the EN pin can
also be externally pulled high by adding a R
EN
resistor
and C
EN
capacitor from the VIN pin (see Figure 1).
RT7277
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OUT OUT
L
IN
VV
I = 1
fL V
⎡⎤
Δ×
⎢⎥
×
⎣⎦
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
highest efficiency operation. However, it requires a large
OUT OUT
L(MAX) IN(MAX)
VV
L = 1
fI V
⎡⎤
×−
⎢⎥
×Δ
⎣⎦
Input and Output Capacitors Selection
The input capacitance, C
IN
, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
A low ESR input capacitor with larger ripple current rating
should be used for the maximum RMS current. The RMS
current is given by :
OUT
IN
RMS OUT(MAX)
IN OUT
V
V
I = I 1
VV
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/ 2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. For the
input capacitor, two 10μF and 0.1μF low ESR ceramic
capacitors are recommended.
The selection of C
OUT
is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for C
OUT
selection to ensure that the control loop is stable.
The output ripple, ΔV
OUT
, is determined by :
Output Voltage Setting
The resistive divider allows the FB pin to sense the output
voltage as shown in Figure 4.
Under Voltage Lockout Protection
The RT7277 has Under Voltage Lockout Protection (UVLO)
that monitors the voltage of PVCC pin. When the V
PVCC
voltage is lower than UVLO threshold voltage, the RT7277
will be turned off in this state. This is non-latch protection.
Over Temperature Protection
The RT7277 equips an Over Temperature Protection (OTP)
circuitry to prevent overheating due to excessive power
dissipation. The OTP will shut down switching operation
when junction temperature exceeds 150°C. Once the
junction temperature cools down by approximately 20°C
the main converter will resume operation. To keep operating
at maximum, the junction temperature should be prevented
from rising above 150°C.
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and an output
voltage. The ripple current ΔI
L
increases with higher V
IN
and decreases with higher inductance.
Figure 4. Output Voltage Setting
The output voltage is set by an external resistive divider
according to the following equation. It is recommended to
use 1% tolerance or better divider resistors.
)
OUT
R1
V = 0.765(1
R2
×+
GND
FB
R1
R2
V
OUT
RT7277
inductor to achieve this goal. For the ripple current
selection, the value of ΔI
L
= 0.2(I
MAX
) will be a reasonable
starting point. The largest ripple current occurs at the
highest V
IN
. To guarantee that the ripple current stays
below the specified maximum, the inductor value should
be chosen according to the following equation :
OUT L
OUT
1
VIESR
8fC
⎡⎤
Δ≤Δ +
⎢⎥
⎣⎦
The output ripple will be highest at the maximum input
voltage since ΔI
L
increases with input voltage. Multiple
capacitors placed in parallel may need to meet the ESR
and RMS current handling requirements.
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
RT7277
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Figure 5. External Bootstrap Diode
PVCC Capacitor Selection
Decouple with a 1μF ceramic capacitor. X7R or X5R grade
dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Over Current Protection
When the output shorts to ground, the inductor current
decays very slowly during a single switching cycle. An
over current detector is used to monitor inductor current
to prevent current runaway. The over current detector
monitors the voltage between SW and GND during the
low side MOS turn-on state. This is cycle-by-cycle
protection. The over current detector also supports
temperature compensated.
SW
BOOT
5V
RT7277
0.1µF
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. A sudden inrush of current through the long
wires can potentially cause a voltage spike at V
IN
large
enough to damage the part.
External Bootstrap Diode
Connect a 0.1μF low ESR ceramic capacitor between the
BOOT and SW pins. This capacitor provides the gate driver
voltage for the high side MOSFET. It is recommended to
add an external bootstrap diode between an external 5V
and the BOOT pin for efficiency improvement when input
voltage is lower than 5.5V or duty ratio is higher than 65%.
The bootstrap diode can be a low cost one such as 1N4148
or BAT54. The external 5V can be a 5V fixed input from
system or a 5V output of the RT7277. Note that the external
boot voltage must be lower than 5.5V
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance,
θ
JA
, is 49°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at
T
A
= 25°C can be calculated by the following formulas :
P
D(MAX)
= (125°C 25°C) / (49°C/W) = 2.041W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curve in Figure 6 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 6. Derating Curve of Maximum Power Dissipation
0.0
0.5
1.0
1.5
2.0
2.5
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB

RT7277GSP

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IC REG BUCK ADJUSTABLE 3A 8SOP
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