PACVGA201QR

Semiconductor Components Industries, LLC, 2011
October, 2011 Rev. 4
1 Publication Order Number:
PACVGA201/D
PACVGA201
VGA Port Companion Circuit
Product Description
The PACVGA201 provides seven channels of ESD protection for
all signal lines commonly found in a VGA port. ESD protection is
implemented with currentsteering diodes designed to safely handle
the high surge currents encountered with IEC6100042 Level4
ESD Protection (8 kV contact discharge). When a channel is
subjected to an electrostatic discharge, the ESD current pulse is
diverted via the protection diodes into the positive supply rail or
ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO,
DDC_OUT and SYNC channels to facilitate interfacing with
lowvoltage video controller ICs and to provide design flexibility in
multiplesupplyvoltage environments.
An internal diode (D
1
, in schematic below) is provided such that
V
CC2
is derived from V
CC3
(V
CC2
does not require an external power
supply input). In applications where V
CC3
may be powered down,
diode D
1
blocks any DC current path from the DDC_OUT pins back to
the powered down V
CC3
rail via the upper ESD protection diodes.
Two noninverting drivers provide buffering for the HSYNC and
VSYNC signals from the Video Controller IC (SYNC_IN1,
SYNC_IN2). These buffers accept TTL input levels and convert them
to CMOS output levels that swing between Ground and V
CC3
.
When the PWR_UP input is driven LOW, the SYNC outputs are
driven LOW and the SYNC inputs can float: no current will be drawn
from the V
CC3
supply.
The PACVGA201 is housed in a 16pin QSOP package with RoHS
compliant leadfree finishing.
Features
Seven Channels of ESD Protection for All VGA Port Connector
Pins
Meets IEC6100042 Level4 ESD Requirements
(8 kV Contact Discharge)
Very Low Loading Capacitance from ESD Protection Diodes on
VIDEO Lines, 4pF Typical
TTL to CMOS LevelTranslating Buffers with Power Down
Mode for HSYNC and VSYNC Lines
Three Power Supplies for Design Flexibility
Compact 16Pin QSOP Package
These Devices are PbFree and are RoHS Compliant
Applications
ESD Protection and Termination Resistors for VGA (Video) Port
Interfaces
Desktop PCs
Notebook Computers
LCD Monitors
http://onsemi.com
MARKING DIAGRAM
Device Package Shipping
ORDERING INFORMATION
PACVGA201QR QSOP16
(PbFree)
2500/Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
QSOP16
QR SUFFIX
CASE 492
PACVGA 201QR = Specific Device Code
YY = Year
WW = Work Week
G = PbFree Package
PACVGA
201QR
YYWWG
PACVGA201
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2
SIMPLIFIED ELECTRICAL SCHEMATIC
GND
VIDEO_3
VIDEO_2
VIDEO_1
V
CC1
DDC_OUT1
V
CC2
R
P
SD1
1
GND
DDC_OUT2
SYNC_IN1
SYNC_IN2
GND
V
CC3
SD2
SYNC_OUT2
SYNC_OUT1
PWR_UP
R
B
D
1
8
9
10
11
13
15
16
14
12
7
6
5
4
3
2
PACKAGE / PINOUT DIAGRAMS
16Pin QSOP
V
CC3
1
2
3
9
16
Top View
SD2
4
5
6
7
8
10
11
12
13
15
14
V
CC1
VIDEO_1
VIDEO_2
VIDEO_3
GND
PWR_UP
V
CC2
SD1
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT1
DDC_OUT2
PACVGA201
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3
Table 1. PIN DESCRIPTIONS
Pin(s) Name Description
1 V
CC3
V
CC3
supply pin. This is an isolated supply input for the two sync buffers and SD1 and SD2 ESD
protection circuits.
2 V
CC1
V
CC1
supply pin. This is an isolated supply pin for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD
protection circuits.
3 VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA
controller device and the video connector.
4 VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA
controller device and the video connector.
5 VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA
controller device and the video connector.
6 GND Ground reference supply pin.
7 PWR_UP Enables the sync buffers when high. When PWR_UP is low the sync outputs are forced low and the
inputs can be floated.
8 V
CC2
V
CC2
supply pin. This is an isolated supply pin for the DDC_OUT1 and DDC_OUT2 ESD protection
circuits. Internally, V
CC2
is derived from the V
CC3
input if the V
CC2
input is not connected to a supply
voltage.
9 DDC_OUT1 DDC_OUT1 ESD protection channel.
10 DDC_OUT2 DDC_OUT2 ESD protection channel.
11 SYNC_IN1 Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines.
12 SYNC_OUT1 Sync signal buffer output. Connects to the video connector side of one of the sync lines.
13 SYNC_IN2 Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines.
14 SYNC_OUT2 Sync signal buffer output. Connects to the video connector side of one of the sync lines.
15 SD1 ESD protection channel input.
16 SD2 ESD protection channel input.
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
V
CC1
, V
CC2
and V
CC3
Supply Voltage Inputs [GND 0.5] to +6.0 V
Diode Forward Current (One Diode Conducting at a Time) 20 mA
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
[GND 0.5] to [V
CC1
+ 0.5]
[GND 0.5] to [V
CC2
+ 0.5]
[GND 0.5] to [V
CC3
+ 0.5]
V
Operating Temperature Range 0 to +70 C
Storage Temperature Range 65 to +150 C
Package Power Rating 750 mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

PACVGA201QR

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Management Specialized - PMIC ESD Net VGA Port Companion Circuit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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