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PACVGA201QR

P1-P3P4-P6
PACVGA201
http://onsemi.com
4
SPECIFICATIONS (Cont’d)
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter Conditions Min Typ Max Units
I
CC1
V
CC1
Supply Current V
CC1
= 5.0 V 10
mA
I
CC3
V
CC3
Supply Current
V
CC3
= 5 V, SYNC Inputs at GND
or V
CC3
, PWR_UP pin at V
CC3
,
SYNC Outputs Unloaded
10
mA
V
CC3
= 5 V, SYNC Inputs at 3.0 V,
PWR_UP Pin at V
CC3
, SYNC
Outputs Unloaded
200
mA
V
CC3
= 5 V, PWR_UP Input at
GND, SYNC Outputs Unloaded
10
mA
V
CC2
V
CC2
Pin Open Circuit Voltage V
CC2
Voltage Internally Derived
from V
CC3
via Diode D1,
No External Current Drawn
[V
CC3
− 0.80] V
V
IH
Logic High Input Voltage V
CC3
= 5 V (Note 2) 2.0 V
V
IL
Logic Low Input Voltage V
CC3
= 5 V (Note 2) 0.8 V
V
OH
Logic High Output Voltage I
OH
= −4 mA, V
CC3
= 5.0 V (Note 3) 4.4 V
V
OL
Logic Low Output Voltage I
OL
= 4 mA, V
CC3
= 5.0 V (Note 3) 0.4 V
R
B,
R
P
Resistor Value PWR_UP = V
CC3
= 5.0 V 0.5 1 2
MW
I
IN
Input Current
VIDEO_x Pins
HSYNC, VSYNC Pins
V
CC1
= 5.0 V, V
IN
= V
CC1
or GND
V
CC3
= 5.0 V, V
IN
= V
CC3
or GND
1
1
mA
C
IN
Input Capacitance on
VIDEO_1, VIDEO_2 and VIDEO_3
Pins
V
CC1
= 5.0 V, V
IN
= 2.5 V,
Measured at 1 MHz
V
CC1
= 2.5 V, V
IN
= 1.25 V,
Measured at 1 MHz
4
4.5
pF
t
PLH
SYNC Buffer L H Propagation Delay C
L
= 50 pF, V
CC3
= 5.0 V,
Input t
R
and t
F
5ns
8 12 ns
t
PHL
SYNC Buffer H L Propagation Delay C
L
= 50 pF, V
CC3
= 5.0 V,
Input t
R
and t
F
5ns
8 12 ns
t
R,
t
F
SYNC Buffer Output Rise & Fall Times C
L
= 50 pF, V
CC3
= 5.0 V,
Input t
R
and t
F
5ns
7.0 ns
V
ESD
ESD Withstand Voltage V
CC1
= V
CC2
= V
CC3
= 5 V (Note 4) 8 kV
1. All parameters specified over standard operating conditions unless otherwise noted.
2. These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP.
3. These parameters apply only to SYNC_OUT1 and SYNC_OUT2.
4. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. V
CC1
, V
CC2
and V
CC3
must be bypassed to GND
via a low impedance ground plane with a 0.2 mF or greater, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied
between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2,
VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard
2 kV per the Human Body model (MIL−STD−883, Method 3015).
PACVGA201
http://onsemi.com
5
APPLICATION INFORMATION
Figure 1. Typical Connection Diagram
11
GND
H−Sync
Video Controller
V−Sync
DDC_Data
DDC_Clk
Red
Green
Blue
H−Sync
V−Sync
DDC_Data
DDC_Clk
Red
Green
Blue
Video Connector
SYNC_IN1
SYNC_IN2
DDC_OUT2
DDC_OUT1
VIDEO_1
VIDEO_2
VIDEO_3
SYNC_OUT1
SYNC_OUT2
GND
PWR_UP
PACVGA201
13
10
9
3
4
5
281
6
7
12
14
To Video
DAC V
CC
5 V
0.2 mF 0.2 mF
SF**
VF**
SF**
VF**
VF**
VF** − VIDEO EMI Filter
SF** − SYNC EMI Filter
V
CC1
V
CC2
V
CC3
15
16
0.2 mF
SD1
SD2
A resistor may be necessary between the V
CC2
pin and ground if protection against a stream of ESD pulses is required while
the PACVGA201 is in the power−down state. The value of this resistor should be chosen such that the extra charge deposited
into the V
CC2
bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD
repetition rate specified by the IEC−61000−4−2 standard is one pulse per second. When the PACVGA201 is in the power−up
state, an internal discharge resistor is connected to ground via a FET switch for this purpose.
For the same reason, V
CC1
and V
CC3
may also require bypass capacitor discharging resistors to ground if there are no other
components in the system to provide a discharge path to ground.
PACVGA201
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6
PACKAGE DIMENSIONS
QSOP16
CASE 492−01
ISSUE A
E
M
0.25 C
A1
A2
C
DETAIL A
DETAIL A
h x 45
_
DIM MAXMIN
INCHES
A 0.053 0.069
b 0.008 0.012
L 0.016 0.050
e 0.025 BSC
h 0.009 0.020
c 0.007 0.010
A1 0.004 0.010
M 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.005 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.005 PER SIDE. D AND E1 ARE
DETERMINED AT DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
__
b
L
6.40
16X
0.42
16X
1.12
0.635
DIMENSIONS: MILLIMETERS
16
PITCH
SOLDERING FOOTPRINT
9
18
D
D
16X
SEATING
PLANE
0.10 C
E1
A
A-B D
0.20
C
e
18
16 9
16X
C
M
D 0.193 BSC
E 0.237 BSC
E1 0.154 BSC
L2 0.010 BSC
D
0.25
C D
B
0.20 C D
2X
2X
2X 10 TIPS
0.10 C
H
GAUGE
PLANE
C
A2 0.049 ----
1.35 1.75
0.20 0.30
0.40 1.27
0.635 BSC
0.22 0.50
0.19 0.25
0.10 0.25
0 8
__
4.89 BSC
6.00 BSC
3.90 BSC
0.25 BSC
1.24 ----
MAXMIN
MILLIMETERS
L2
A
SEATING
PLANE
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
PACVGA201/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
P1-P3P4-P6

PACVGA201QR

Mfr. #:
Buy PACVGA201QR
Manufacturer:
ON Semiconductor
Description:
Power Management Specialized - PMIC ESD Net VGA Port Companion Circuit
Lifecycle:
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