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MC100EP196BMNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MC100EP196B
http://onsemi.com
13
An expansion of the latch section of the block diagram is
pictured in Figure 8. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
of chip #1 in Figure 7 is LOW this device’s
CASCADE output will also be low while the CASCADE
output will be high. In this condition the SET MIN pin of
chip #2 will be asserted HIGH and thus all of the latches of
chip #2 will be reset and the device will be set at its minimum
delay.
Chip #1, on the other hand, will have both SET MIN and
SET MAX deasserted so that its delay will be controlled
entirely by the address bus A0—A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0—A9 address bus) D10 will be
asserted to signal the need to cascade the delay to the next
EP196B device. When D10 is asserted, the SET MIN pin of
chip #2 will be deasserted and SET MAX pin asserted
resulting in the device delay to be the maximum delay.
Table 12 shows the delay time of two EP196B chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 7. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
SET
MIN
SET
MAX
TO SELECT MULTIPLEXERS
BIT 0
D0 Q0
LEN
Set Reset
BIT 1
D1 Q1
LEN
Set Reset
BIT 2
D2 Q2
LEN
Set Reset
BIT 3
D3 Q3
LEN
Set Reset
BIT 4
D4 Q4
LEN
Set Reset
BIT 5
D5 Q5
LEN
Set Reset
BIT 6
D6 Q6
LEN
Set Reset
BIT 7
D7 Q7
LEN
Set Reset
BIT 8
D8 Q8
LEN
Set Reset
BIT 9
D9 Q9
LEN
Set Reset
Figure 8. Expansion of the Latch Section of the EP196B Block Diagram
MC100EP196B
http://onsemi.com
14
Table 12. Delay Value of Two EP196B Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps
0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps
0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps
0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps
0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps
0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps
0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps
0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps
0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps
0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps
0 0 0 0 0 1 0 0 0 0 0 220 ps 4720 ps
0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps
0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps
0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps
0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps
0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps
1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps
1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps
1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps
1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps
1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps
1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps
1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps
1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps
1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps
1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps
1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps
1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps
1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps
1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps
1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps
MC100EP196B
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15
Multi−Channel Deskewing
The most practical application for EP196B is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
be sent through each EP196B as shown in Figure 9. One signal
channel can be used as reference and the other EP196Bs can
be used to adjust the delay to eliminate the timing skews.
Nearly any high−speed system can be fine−tuned (as small as
10 ps) to reduce the skew to extremely tight tolerances.
EP196B
IN Q
IN
Q
#1
EP196B
IN Q
IN
Q
#2
EP196B
IN Q
IN
Q
#N
Digital
Data
Control
Logic
Figure 9. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
EP196Bs provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP196Bs and EP31 as shown in Figure
10, the delay can be measured. The first EP196B can be set
to SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP196B is triggered along with the first
EP196B and its output provides a clock signal for EP31.
The programmed delay of the second EP196B is varied to
detect the output edge from the unknown delay device.
If the programmed delay through the second EP196B is too
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP196B is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP196B, the flip−flop will bounce between logic high and
logic low. The digital code in the second EP196B can be
directly correlated into an accurate device delay.
EP196B
IN Q
IN
Q
#1
EP196B
IN Q
IN
Q
#2
Unknown Delay
Device
Control
Logic
D
CLK
Q
Q
EP31
CLOCK
CLOCK
Figure 10. Multiple Channel Deskewing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MC100EP196BMNG

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Buy MC100EP196BMNG
Manufacturer:
ON Semiconductor
Description:
Delay Lines / Timing Elements PROGR DELAY CHIP DIODE 3.3V
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