MC100EP196B
http://onsemi.com
4
Table 2. CONTROL PIN
Pin State Function
EN
LOW (Note 3) Input Signal is Propagated to the Output
HIGH Output Holds Logic Low State
LEN
LOW (Note 3) Transparent or LOAD mode for real time delay values present on D[0:10].
HIGH LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
SETMIN
LOW (Note 3) Output Delay set by D[0:10]
HIGH Set Minimum Output Delay
SETMAX
LOW (Note 3) Output Delay set by D[0:10]
HIGH Set Maximum Output Delay
D10
LOW (Note 3) CASCADE Output LOW, CASCADE Output HIGH
HIGH CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
V
CF
V
EF
Pin (Note 4) ECL Mode
V
CF
No Connect LVCMOS Mode
V
CF
1.5 V $ 100 mV LVTTL Mode (Note 5)
4. Short V
CF
(pin 8) and V
EF
(pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R
CF
(suggested resistor value
is 2.2 kW $5%), between V
CF
and V
EE
pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
POWER SUPPLY
CONTROL DATA SELECT INPUTS PINS (D [0:10])
LVCMOS LVTTL LVPECL LVNECL
PECL Mode Operating Range YES YES YES N/A
NECL Mode Operating Range N/A N/A N/A YES
Table 5. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor (R1)
75 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6) Pb−Free Pkg
QFN−32
LQFP−32
Level 1
Level 2
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 1237 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
