4 AT88SC6416C
5015KS–SMEM–08/09
3. *Absolute Maximum Ratings
Operating Temperature.............................40°C to +85°C
Storage Temperature ............................65°C to + 150°C
Voltage on Any Pin
with Respect to Ground ....................... 0.7 to V
CC
+0.7V
Maximum Operating Voltage.......................................6.0V
DC Output Current ..................................................5.0 mA
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other condition beyond those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods of time may affect device
reliability.
Table 2. DC Characteristics
Applicable over recommended operating range from V
CC
= +2.7 to 5.5V, T
AC
= -40°C to +85°C (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
V
CC
(2)
Supply Voltage 2.7 5.5 V
I
CC
Supply Current (V
CC
= 5.5V) Async READ at 3.57MHz 5 mA
I
CC
Supply Current (V
CC
= 5.5V) Async WRITE at 3.57MHz 5 mA
I
CC
Supply Current (V
CC
= 5.5V) Synch READ at 1MHz 5 mA
I
CC
Supply Current (V
CC
= 5.5V) Synch WRITE at 1MHz 5 mA
I
SB
Standby Current (V
CC
= 5.5V) V
IN
= V
CC
or GND 1 mA
V
IL
(1)
SDA/IO Input Low Threshold 0 V
CC
x 0.2 V
V
IL
(1)
SCL/CLK Input Low Threshold 0 V
CC
x 0.2 V
V
IL
(1)
RST Input Low Threshold 0 V
CC
x 0.2 V
V
IH
(1)(2)
SDA/IO Input High Threshold V
CC
x 0.7 V
CC
V
V
IH
(1)(2)
SCL/CLK Input High Threshold V
CC
x 0.7 V
CC
V
V
IH
(1)(2)
RST Input High Threshold V
CC
x 0.7 V
CC
V
I
IL
SDA/IO Input Low Current 0 < V
IL
< V
CC
x 0.15 15
μA
I
IL
SCL/CLK Input Low Current 0 < V
IL
< V
CC
x 0.15 15
μA
I
IL
RST Input Low Current 0 < V
IL
< V
CC
x 0.15 50
μA
I
IH
SDA/IO Input High Current V
CC
x 0.7 < V
IH
< V
CC
20
μA
I
IH
SCL/CLK Input High Current V
CC
x 0.7 < V
IH
< V
CC
100
μA
I
IH
RST Input High Current V
CC
x 0.7 < V
IH
< V
CC
150
μA
V
OH
SDA/IO Output High Voltage 20K ohm external pull-up V
CC
x 0.7 V
CC
V
V
OL
SDA/IO Output Low Voltage I
OL
= 1mA 0 V
CC
x 0.15 V
I
OH
SDA/IO Output High Current V
OH
20
μA
Notes: 1. V
IL
min and V
IH
max are reference only and are not tested.
2. To prevent Latch Up Conditions from occurring during Power Up of the AT88SCxxxxC, V
CC
must be turned
on before applying V
IH
. For Powering Down, V
IH
must be removed before turning V
CC
off.
AT88SC6416C
5
5015KS–SMEM–08/09
Table 3. AC Characteristics
Applicable over recommended operating range from V
CC
= +2.7 to 5.5V, T
AC
= -40°C to +85°C, CL = 30pF
(unless otherwise noted)
Symbol Parameter Min Max Units
f
CLK
Async Clock Frequency (V
CC
Range: +4.5 - 5.5V) 1 5 MHZ
f
CLK
Async Clock Frequency (V
CC
Range: +2.7 - 3.3V) 1 4 MHZ
f
CLK
Synch Clock Frequency 0 1 MHZ
Clock Duty cycle 40 60 %
t
R
Rise Time - I/O, RST 1
μS
t
F
Fall Time - I/O, RST 1
μS
t
R
Rise Time – CLK 9% x period
μS
t
F
Fall Time – CLK 9% x period
μS
t
AA
Clock Low to Data Out Valid 35 nS
t
HD.STA
Start Hold Time 200 nS
t
SU.STA
Start Set-up Time 200 nS
t
HD.DAT
Data In Hold Time 10 nS
t
SU.DAT
Data In Set-up Time 100 nS
t
SU.STO
Stop Set-up Time 200 nS
t
DH
Data Out Hold Time 20 nS
t
WR
Write Cycle Time (at 25°C) 5 mS
t
WR
Write Cycle Time (-40° to +85°C) 7 mS
4. Device Operation for Synchronous Protocols
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see Figure 5 on page 7). Data changes
during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 6 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see Figure 6 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a zero to acknowledge that it has received each word. This
happens during the ninth clock cycle.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
6 AT88SC6416C
5015KS–SMEM–08/09
Figure 3. Bus Timing for 2 wire communications: SCL: Serial Clock, SDA – Serial Data I/O
SCL
SDA IN
S
DA OUT
t
F
t
HIGH
t
LOW
t
LOW
t
R
t
AA
t
DH
t
BUF
t
SU.STO
t
SU.DAT
t
HD.DAT
t
HD.STA
t
SU.STA
Figure 4. Write Cycle Timing: SCL: Serial Clock, SDA – Serial Data I/O
t
wr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
Note: The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.

AT88SC6416C-MJ

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
Security ICs / Authentication ICs CRYPTO Memory 64Kbit, 16zones
Lifecycle:
New from this manufacturer.
Delivery:
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